Where DFT Sits in the RTL-to-Silicon Flow

Chapter 0 · Section 0.3 · DFT Foundations

Project thread — we push the single D flip-flop through the whole flow: RTL → synth → scan insertion → ATPG → gate sim → silicon test, and watch the artifacts it produces at each stage. 0.4 explains the reachability (controllability/observability) that every stage serves.

1. Why Should I Learn This?

Knowing where DFT lives tells you when your decisions matter — and they matter early.

• DFT is not one step — it threads RTL → synth → scan → ATPG → gate sim → silicon test.
• Every role touches it — RTL, DV, synthesis, physical design, DFT, test.
• RTL choices cap coverage — testability is a shift-left concern.

If you know the flow, you know who hands what to whom — and where a small early fix saves a late-stage crisis.

2. Real Silicon Story — the testability problem found too late

A block was thrown "over the wall" to DFT after RTL freeze. At scan insertion, DRC flagged a batch of flops on an uncontrollable internally-generated clock — they couldn't be put on a scan chain. ATPG coverage came in far below signoff, and closing it required an RTL change (make the clock test-controllable) — an expensive late respin of RTL, synthesis, and floorplan.

Had the RTL engineer known the flow — that scan needs controllable clocks/resets (Chapter 4) — the one-line RTL fix would have cost minutes at design time instead of weeks at signoff.

Lesson: DFT threads through the whole flow, and RTL decisions bound downstream coverage. Fix testability early (shift-left); discovering it at scan/ATPG is the expensive path.

3. Concept — the flow, the roles, the artifacts

The six stages (and what DFT does in each):

The artifacts handed between stages:

• Netlist (synth → scan) — the gate-level design to make testable.
• Scan-insertion report (scan → ATPG) — chains built, DRC results, flops converted.
• ATPG pattern + coverage report (ATPG → gate sim / tester) — the patterns and the test coverage achieved.
• Tester log (silicon test → yield/quality) — per-die pass/fail + bin (0.2).

The through-line (why RTL matters most):

• Each stage consumes the previous stage's artifact and is bounded by it.
• Untestable RTL produces a netlist scan can't fully reach → ATPG can't build patterns for it → coverage caps low → escapes.
• So the RTL engineer's choices set a ceiling on what the entire downstream flow can achieve — DFT is shift-left.

4. Mental Model — a relay race with a baton per leg

The flow is a relay race, and the artifact is the baton passed at each handoff.

• Each runner (stage) receives a baton (the previous artifact), runs their leg (does their job), and passes a new baton (their artifact) to the next.
• RTL hands off the design intent (as RTL); synthesis hands off the netlist; scan hands off the scanned netlist + report; ATPG hands off the patterns + coverage; test hands off the verdict.
• If the first runner starts slow (untestable RTL), no later runner can make up the time — the coverage ceiling is set at the start.
• That's why the first leg (RTL) is decisive: the whole race is bounded by how well the baton was handed off at the start.

Pass a good baton early (testable RTL), and every downstream leg can do its job; a bad first baton caps the whole race.

5. Working Example — the DFF through the flow, with its artifacts

Push the project's flip-flop through the flow and watch the artifacts appear.

RTL → Synthesis → a netlist (a representative flop cell):

// After synthesis — REPRESENTATIVE netlist (an ordinary flop, not yet scan)
module dff (clk, rst_n, d, q);
  input clk, rst_n, d; output q;
  DFFRX1 u_q (.D(d), .CK(clk), .RN(rst_n), .Q(q));   // ordinary reset flop -- scan insertion will convert it
endmodule

Scan insertion → a scan flop + a scan-insertion report:

// After scan insertion — REPRESENTATIVE: the flop is now a SCAN flop (mux-D), on a chain (Ch3)
module dff (clk, rst_n, d, q, scan_in, scan_en, scan_out);
  input clk, rst_n, d, scan_in, scan_en; output q, scan_out;
  SDFFRX1 u_q (.D(d), .SI(scan_in), .SE(scan_en), .CK(clk), .RN(rst_n), .Q(q));  // functional D vs scan-in SI
  assign scan_out = q;   // this flop's Q feeds the chain out (or the next flop's SI)
endmodule

# Scan-insertion report — REPRESENTATIVE (handed from scan → ATPG):
  Flops total ............ 1
  Scan flops ............. 1  (100% converted)
  Scan chains ............ 1  (length 1)
  Scan DRC violations .... 0
  Uncontrolled clocks .... 0   (clk is test-controllable)
# -> ATPG can now CONTROL d (via scan-in) and OBSERVE q (via scan-out) directly.

ATPG → patterns + a coverage report:

# ATPG coverage report — REPRESENTATIVE (handed from ATPG → gate sim / tester):
  Fault model ............ stuck-at
  Total faults ........... 6
  Detected .............. 6
  Test coverage ......... 100.00%   (this tiny flop, fully controllable/observable, is fully testable)
  Patterns .............. 3
# -> because scan gave full controllability + observability, ATPG reached 100% (contrast: buried flop, 0.1)

6. Industry Flow — the artifacts handed between stages

The stages don't just run in sequence — they hand artifacts to each other, and each is bounded by what it receives:

7. Debugging Session — a late testability problem that RTL should have owned

8. Common Mistakes

• Treating DFT as one late step. It threads through every stage — testability starts in RTL.
• Throwing RTL over the wall to DFT. Late testability problems need RTL respins (expensive).
• Ignoring the scan-insertion and coverage reports. They're your testability scoreboard — read them early.
• Assuming ATPG can fix untestable RTL. ATPG is bounded by controllability/observability the RTL/scan provide.
• Confusing gate sim (verify patterns) with functional verification. Gate sim here checks the patterns, not the design's intent.

9. Industry Best Practices

• Shift testability left — scan-friendly RTL, early scan DRC, early coverage estimates.
• Know the artifact handoffs — netlist, scan report, patterns+coverage, tester log.
• Read the reports as a designer — DRC violations and low coverage trace to your RTL.
• Plan DFT in the schedule — scan, ATPG, coverage closure are milestones, not afterthoughts.
• Keep roles clear — RTL testability, DFT scan/ATPG, DV/gate-sim pattern verification, test on the ATE.

10. Senior Engineer Thinking

• Beginner: "DFT is the scan/ATPG box near tape-out."
• Senior: "DFT is everywhere in the flow, and my RTL sets the ceiling. Are my clocks/resets test-controllable? What will scan DRC and ATPG coverage say? I read those reports early — a testability problem is cheap in RTL and brutal at signoff."

The senior treats testability as an RTL property, reads the DFT reports early, and shifts left.

11. Silicon Impact

The flow's structure — each stage bounded by the previous artifact — makes the RTL stage decisive. Testable RTL flows cleanly through scan, ATPG, and test to high coverage and caught defects; untestable RTL sets a low coverage ceiling that no downstream effort can raise, forcing either escapes (defects to the field, Chapter 1) or expensive late respins. Because the scan-insertion and coverage reports trace low coverage directly back to RTL choices, the RTL engineer holds real leverage — and reading those reports early (shift-left) converts a signoff crisis into a design-time tweak. Understanding where DFT sits is therefore not org-chart trivia: it's the map that tells every role when their decisions bound the outcome — and for RTL, that's at the very start.

12. Engineering Checklist

• Placed DFT across the whole flow (RTL → synth → scan → ATPG → gate sim → silicon test).
• Identified the artifacts and their owners/consumers (netlist, scan report, patterns+coverage, tester log).
• Recognized RTL choices cap downstream coverage — shift testability left.
• Read the scan-insertion and coverage reports as a testability scoreboard.
• Distinguished gate sim (verify patterns) from functional verification.

13. Try Yourself

1. Take the DFF and trace it through the flow: write the RTL, the post-synth netlist (ordinary flop), the post-scan scan flop, and imagine the scan-insertion and ATPG coverage reports.
2. Observe: with scan, ATPG reaches high coverage (the flop is fully controllable/observable).
3. Change: give the flop an internally-generated, uncontrolled clock; note that scan DRC would flag it and coverage would drop — a testability problem visible only downstream.
4. Fix: make the clock test-controllable in the RTL and see the ceiling rise. That's shift-left.

The flow and artifacts are tool-independent concepts; any synthesis/scan/ATPG toolchain follows this shape. No paid tool required to learn the flow.

14. Interview Perspective

• Weak: "DFT is scan insertion and ATPG."
• Good: "DFT runs through RTL, synthesis, scan insertion, ATPG, gate sim, and silicon test — each stage does its part."
• Senior: "DFT threads through the whole flow, and each stage is bounded by the previous artifact: the netlist bounds scan, scan bounds ATPG, ATPG bounds coverage. So the RTL engineer's choices cap the coverage the entire flow can reach — testability is a shift-left property. I read the scan-insertion and coverage reports early because a testability problem is a one-line RTL fix at design time and a respin at signoff. The flow tells you when each role's decisions matter — for RTL, that's at the start."

15. Interview / Review Questions

16. Key Takeaways

• DFT is not one step — it threads through the entire flow: RTL → synthesis → scan insertion → ATPG → gate simulation → silicon test, with DFT work in each stage.
• Each stage consumes the previous stage's artifact and is bounded by it — netlist → scan → patterns+coverage → tester log — so a weak input caps the output.
• The artifacts are concrete: the netlist (synth), the scan-insertion report (chains/DRC), the ATPG pattern + coverage report, and the tester log (pass/fail per die) — each with an owner who generates it and a consumer who reads it.
• RTL choices cap the coverage the whole flow can reach — testability is a shift-left, whole-team property; a problem cheap to fix in RTL is expensive to fix at scan/ATPG signoff.
• Read the scan-insertion and coverage reports as your testability scoreboard — DRC violations and low coverage trace back to your RTL; gate sim here verifies the patterns, not the design's function. Next: 0.4 — testability: controllability & observability.

17. Quick Revision

DFT threads through the WHOLE flow: RTL → synth → scan insertion → ATPG → gate sim → silicon test. Artifacts flow stage→stage (netlist → scan-insertion report → patterns + coverage report → tester log), each stage bounded by its input. So RTL choices CAP coverage — testability is shift-left; a fix that's one line in RTL is a respin at signoff. Read the scan/coverage reports early. Gate sim here verifies patterns, not function. Next: 0.4 — controllability & observability.