UVM RAL · Chapter 11 · Debugging RAL

Production Debug Checklist

This capstone turns everything the debugging chapter taught into a standing checklist you run on every RAL project, so bugs are prevented at bring-up instead of chased across weeks of scattered failures. It has two parts. The bring-up gates run first, before you trust any result: confirm the model is built and locked, verify every HDL path resolves so the backdoor is proven, connect the predictor with exactly one prediction mode active, verify the adapter round trip including status by forcing a bus error, check reset values, and enable coverage through both gates. Each gate is a cheap check that closes off a whole class of downstream failure. The second part is a debug routine for when something fails: triage category first using breadth and frontdoor versus backdoor, then apply the matching within-category method. This lesson breaks a project that skipped the HDL-path gate and paid for it later.

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Chapter 11 · Section 11.6 · Debugging RAL

1. Why Should I Learn This?

Every failure class in this chapter has a cheap up-front check that catches it at bring-up — and skipping those checks is what turns a day-one catch into a weeks-later hunt across scattered failures. A standing checklist that runs the bring-up gates first and triages failures category-first is what converts the chapter's methods from reactive firefighting into proactive prevention — the single highest-leverage practice for a RAL project.

Learning the production checklist operationalizes the whole track: it sequences the bring-up gates that pre-empt the six mistake categories (11.5) and wires in the category-first triage and within-category methods (11.1–11.4) as the standing debug routine. It is the chapter's — and the track's — practical close.

2. Industry Story — the gate that would have cost five minutes

A project skips the HDL-path verification gate at bring-up — 'we'll trust the paths; running the check is a chore.' For weeks, tests use backdoor setup (poke to seed state, 8.4) that silently relies on those unverified paths. Some paths do not resolve; a few resolve to the wrong signal. Nothing fails obviously at first.

Then failures start appearing — scattered across many tests, inconsistent, hard to correlate: a test that backdoor-seeds one register behaves oddly, another silently sets up the wrong state, a checker built on a backdoor read passes a bug through. Each is investigated separately, as its own mystery, over days, because nothing connects them — until someone finally runs the HDL-path check and discovers a swath of registers whose paths never resolved. The single gate (G2) — five minutes with uvm_reg_mem_hdl_paths_seq at bring-up — would have flagged all of them on day one, as one clear report, instead of weeks of scattered symptoms. The cost of skipping the gate was not zero; it was deferred and multiplied. The post-mortem lesson: each bring-up gate is a cheap up-front check that catches a whole category of failure at day one; skipping a gate does not save its cost, it defers and multiplies it — a defect the gate would have caught as one clear report instead surfaces weeks later as scattered, uncorrelated failures across many tests; run the gates first, before trusting any result.

3. Concept — gates first, then category-first triage

The checklist has two parts: prevent at bring-up, then triage when something fails.

Part A — bring-up gates (run first, before trusting any result):
- G1 — Model built and locked. The model is fully built and locked before any use (Lifecycle). Prevents: using an unbuilt/unlocked model.
- G2 — HDL paths verified. uvm_reg_mem_hdl_paths_seq confirms every path resolves — the backdoor is proven (11.4). Prevents: unresolved/wrong-path backdoor bugs.
- G3 — Predictor connected, single mode. The predictor is connected to the monitor and exactly one prediction mode is active (11.2). Prevents: frozen mirror, fighting predictors.
- G4 — Adapter round trip verified, incl. status. Data/address round-trip and a forced bus error confirmed to return UVM_NOT_OK (11.3). Prevents: swallowed errors, byte-lane corruption.
- G5 — Reset values checked. The hardware-reset sequence confirms modelled resets match the DUT (7.4). Prevents: wrong-reset mismatches.
- G6 — Coverage enabled (both gates). include_coverage before build and set_coverage at run (10.1). Prevents: a silent 0%.
Part B — debug routine (when something fails): triage category-first with breadth (one vs many) and frontdoor-vs-backdoor (bus path vs storage vs model) to land in the right category (11.5), then apply the within-category method (11.1–11.4).
The economics: a gate is cheap and up-front; skipping it defers and multiplies the cost into scattered late failures. Run gates first.

Here is the checklist as a routine — gates in order, then the debug loop:

Figure 1 — the production RAL checklist. Run the BRING-UP GATES first, in order, before trusting any result: G1 model built+locked, G2 HDL paths verified (backdoor proven, 11.4), G3 predictor connected + single mode (11.2), G4 adapter round-trip incl. forced-error status (11.3), G5 reset values checked (7.4), G6 coverage enabled both gates (10.1). Each is a cheap check that prevents a whole failure category. THEN, when something fails, run the DEBUG ROUTINE: triage category-first with breadth + frontdoor-vs-backdoor (11.5) and apply the within-category method (11.1-11.4). Skipping a gate does not save its cost — it defers and multiplies it into scattered late failures.

4. Mental Model — gates are cheap insurance; a skipped gate is a deferred, multiplied bill

Mental Model — a bring-up gate is not a chore you can skip to save time; skipping it defers and multiplies the cost

Each bring-up gate is cheap insurance against a whole category of failure. Skipping a gate does not save its cost — it defers the cost to later and multiplies it, converting one clear day-one report into weeks of scattered, uncorrelated hunts.

The tempting error is to see a bring-up gate as a chore — 'running the HDL-path check is tedious, the paths are probably fine, let's skip it and get to testing.' But a gate is not overhead; it is insurance whose premium is minutes and whose payout is catching a whole failure category before anything is built on it. The key insight is about when and how the cost lands. If you run the gate, the cost is small, up-front, and localized: five minutes, one clear report listing exactly what is wrong, fixed before any test depends on it. If you skip the gate, the cost does not disappear — the bugs the gate would have caught are still there, but now they are latent, and they surface later, scattered across many tests as individual mysteries with no obvious common cause. Instead of one report saying 'these ten paths do not resolve,' you get ten separate weird failures over three weeks, each investigated alone, each expensive to trace, none obviously connected — until someone finally runs the check the gate would have run on day one. So skipping the gate defers the cost (to weeks later, when it is far more expensive to trace) and multiplies it (into many scattered investigations instead of one). That is a terrible trade: you pay minutes to save weeks, and skipping inverts it. The mental model, then, is that the order is the point — gates first, before trusting any result — because a gate's entire value is in catching the problem before work is built on the broken assumption. Once tests, setups, and checkers depend on an unverified path or an unconnected predictor, the failure is already diffused; the gate is cheap precisely because it runs before that diffusion.

Two habits:

Run the gates first, before trusting any result. A gate's value is catching a category before anything is built on it — order is the point.
Treat a skipped gate as a deferred, multiplied bill. You don't save the cost, you diffuse it into scattered late failures — pay the minutes up front.

5. Working Example — running the bring-up gates

Run the gates in order at bring-up, each a cheap check that pre-empts a failure category:

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Snippet

// G1 model built + LOCKED, G2 HDL paths verified, G3 predictor connected + single mode.
reg_model.build(); reg_model.lock_model();                        // G1: locked before use
uvm_reg_mem_hdl_paths_seq hp = uvm_reg_mem_hdl_paths_seq::type_id::create("hp");
hp.model = reg_model; hp.start(null);                              // G2: every hdl_path proven (11.4)
mon.ap.connect(predictor.bus_in);                                 // G3: predictor connected (11.2)
predictor.map = reg_model.default_map; predictor.adapter = adapter;   // single prediction mode

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Snippet

// G4 adapter round-trip INCLUDING status: prove data/address round-trip AND that a forced error -> NOT_OK.
uvm_reg_data_t pk, fd; uvm_status_e s;
reg_h.poke(s, 32'hA5A5_1234); reg_h.peek(s, pk); reg_h.read(s, fd);
if (pk !== 32'hA5A5_1234 || fd !== pk) `uvm_error("GATE", "G4 data/address round-trip failed (11.3)")
force_bus_error(reg_h); reg_h.read(s, fd);
if (s != UVM_NOT_OK) `uvm_error("GATE", "G4 STATUS: forced bus error not reported as UVM_NOT_OK (11.3)")

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Snippet

// G5 reset values checked, G6 coverage enabled (both gates).
uvm_reg_hw_reset_seq rst = uvm_reg_hw_reset_seq::type_id::create("rst");
rst.model = reg_model; rst.start(bus_sqr);                        // G5: modelled resets vs DUT (7.4)
uvm_reg::include_coverage("*", UVM_CVR_FIELD_VALS);               // G6 gate 1 (BEFORE build, 10.1)
void'(reg_model.set_coverage(UVM_CVR_FIELD_VALS));               // G6 gate 2 (at run, 10.1)

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Snippet

// PART B — on any later failure, run the DEBUG ROUTINE (do NOT guess the layer):
//   1. breadth: one register or many?  (many -> Prediction/Map/Adapter; one -> Model/Access-method, 11.5)
//   2. frontdoor vs backdoor: bus path vs storage vs model?
//   3. category confirmed -> apply the method: mirror 11.1 / prediction 11.2 / adapter 11.3 / backdoor 11.4

Each gate is a few lines that pre-empts a whole failure category; the debug routine handles whatever slips through. Skipping a gate — say G2 — is the bug of the next section.

6. Debugging Session — a project that skipped the HDL-path gate

Skipping the HDL-path bring-up gate lets backdoor setup silently use unresolved/wrong paths across many tests, surfacing as scattered late failures the gate would have caught on day one

RUN THE GATES FIRST

Buggy Code

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Snippet

// Bring-up SKIPS G2 (HDL-path verification) — 'the paths are probably fine':
reg_model.build(); reg_model.lock_model();
// (missing) uvm_reg_mem_hdl_paths_seq ... hp.start(null);   // G2 SKIPPED
// Tests then rely on backdoor SETUP (poke to seed state, 8.4) using UNVERIFIED paths.
// Some paths don't resolve; a few resolve to the WRONG signal — but nothing fails obviously at first.

Symptom

Weeks into the project, failures appear scattered across many tests — inconsistent, hard to correlate: one test that backdoor-seeds a register behaves oddly, another silently establishes the wrong setup state, a checker built on a backdoor read lets a bug through. Each is investigated separately, as its own mystery, over days, because nothing obviously connects them. There is no single failure pointing at HDL paths — just a diffuse pattern of unreliability that traces back, eventually, to a swath of registers whose backdoor paths never resolved or resolved wrong.

Root Cause

The technical cause is unverified HDL paths (unresolved, or resolving to the wrong signal, 11.4) that backdoor setup silently relied on across many tests — so seeding and backdoor checks were quietly built on nothing or on the wrong storage. The process cause — the real subject of this page — is that the HDL-path bring-up gate (G2) was skipped. That gate, uvm_reg_mem_hdl_paths_seq run once at bring-up, would have validated every path and reported the broken ones on day one, as a single clear list, before any test relied on them. Skipping it did not remove the cost of those broken paths — it deferred the cost to weeks later and multiplied it, converting one up-front report into many scattered, individually-investigated failures with no obvious common cause. The bugs were latent from the start; the missing gate simply let them diffuse into the test suite before surfacing. It is the checklist's core lesson made concrete: the gate's value is catching the category before work is built on the broken assumption.

Fix

Run the skipped gate now — uvm_reg_mem_hdl_paths_seq — to get the single clear report of every unresolved/wrong path, fix them, and re-verify; the scattered failures resolve together. Then institutionalize the gates: run G1–G6 at bring-up, before trusting any result, on every project, so this class of diffuse late failure cannot recur. The method the page teaches: each bring-up gate is a cheap up-front check that catches a whole failure category on day one; skipping a gate does not save its cost, it defers and multiplies it into scattered late failures — run the gates first, before trusting any result. And when something does slip through, use the debug routine (triage category-first with breadth + frontdoor-vs-backdoor, then apply the within-category method) rather than investigating each failure as an unconnected mystery. Gates prevent; the routine cures; together they are the operational form of the whole chapter.

7. Common Mistakes

Skipping bring-up gates to 'save time.' A skipped gate defers and multiplies its cost into scattered late failures — run all six first, before trusting any result.
Trusting backdoor before verifying paths (G2). Unverified paths silently corrupt backdoor setup and checks across many tests (11.4).
Not forcing a bus error to check adapter status (G4). A swallowed-error adapter has no wrong-value symptom — force an error and confirm UVM_NOT_OK (11.3).
Debugging failures as unconnected mysteries. Scattered failures often share one root a gate would have caught — and the debug routine (breadth + frontdoor-vs-backdoor) correlates them.
Running gates after tests already depend on the model. A gate's value is catching a category before work is built on it — order is the point.

8. Industry Best Practices

Institutionalize the six bring-up gates. G1 locked, G2 paths, G3 predictor, G4 adapter+status, G5 resets, G6 coverage — run first, every project.
Force a bus error at bring-up. The only way to verify adapter status fidelity (G4) — a swallowed error is otherwise invisible (11.3).
Verify HDL paths before any backdoor use. uvm_reg_mem_hdl_paths_seq at bring-up (G2) so backdoor setup and checks rest on proven paths (11.4).
Standardize the debug routine. Triage category-first (breadth + frontdoor-vs-backdoor, 11.5), then apply the within-category method (11.1–11.4).
Treat gates as prevention, the routine as cure. Prevent categories at bring-up; correlate and localize whatever slips through — do not debug reactively.

9. Interview / Review Questions

10. Key Takeaways

The production checklist has two parts: bring-up gates (prevent) run first, before trusting any result, and a debug routine (cure) for whatever slips through — the operational form of the whole chapter.
The six gates: G1 model built + locked; G2 HDL paths verified (backdoor proven, 11.4); G3 predictor connected + single mode (11.2); G4 adapter round trip incl. forced-error status (11.3); G5 reset values checked (7.4); G6 coverage enabled both gates (10.1) — each pre-empts a whole failure category.
The debug routine: triage category-first with breadth and frontdoor-vs-backdoor (11.5), then apply the within-category method (mirror 11.1 / prediction 11.2 / adapter 11.3 / backdoor 11.4).
A skipped gate does not save its cost — it defers and multiplies it into scattered, uncorrelated late failures; a gate's value is catching a category before anything is built on the broken assumption, so order is the point.
Together, the gates prevent categories at bring-up and the routine cures what slips through — turning the debug chapter (11.1–11.5) from reactive firefighting into a repeatable process that keeps a RAL project verifying the design, not chasing its own infrastructure.