UVM RAL · Chapter 13 · Production RAL

Auto-Generated RAL

Every register model in this track so far was hand-written, which is the right way to learn RAL but not how production models are built. In production the register model is generated, not hand-written. A machine-readable register specification is the single source of truth, and a generator tool produces multiple artifacts from it: the UVM register model, often the RTL register block, the documentation, and firmware C headers. Because they all come from one spec, they stay consistent by construction. From that follows the master discipline of production RAL: you do not hand-edit the generated model, you edit the spec and regenerate. This page establishes that pipeline and the never-edit-outputs rule, then breaks the signature bug where a hand-edited generated model reverts on the next regeneration and diverges from the spec-driven RTL and headers.

Foundation12 min readUVM RALauto-generatedsource of truthgeneratorspec

Chapter 13 · Section 13.1 · Production RAL

1. Why Should I Learn This?

Production register models are generated, not hand-written, and treating a generated model like hand-written code — editing it directly — is the fastest way to lose your fix (it reverts on regeneration) and diverge from the hardware (which is generated from the same spec you bypassed). Knowing that the spec is the source of truth and generated files are outputs never to be edited is the single most important production-RAL habit; it is what keeps the model, RTL, docs, and firmware all describing the same registers.

Learning auto-generated RAL reframes everything the earlier chapters taught — the hand-written models were for learning; in production the model is a pipeline artifact — and it sets up the spec formats (IP-XACT 13.2, RALF/CSRSpec 13.3) and the integration/guidelines that follow.

2. Industry Story — the fix that vanished overnight

An engineer finds a wrong access policy on a register in the generated UVM model and 'fixes' it by editing the generated file directly — changes RO to RW, commits, tests pass. The next morning, the nightly flow regenerated the model from the spec, and the fix was gone — the file was overwritten, the policy back to RO, and the tests failing again. Confusion: 'I fixed this yesterday.'

The edit was to a generated output, and outputs are regenerated — so the hand-edit was silently overwritten on the next regen. But there was a deeper problem hiding behind the reverted fix: while the hand-edit was in place, the model said RW while the spec (and therefore the RTL and the C headers generated from that spec) still said RO — the model had diverged from the very hardware and software it describes. Even if the edit had not been overwritten, it would have made the model disagree with the RTL. The real question was 'which is correct, RO or RW?' — and that belongs in the spec: fix the spec, regenerate, and the correct policy propagates to the model, the RTL, the docs, and the headers together, consistently, and survives regeneration. The post-mortem lesson: in production RAL the register model is a generated output of a spec-driven pipeline — hand-editing it means the fix is overwritten on the next regeneration and, until then, the model diverges from the spec and from the RTL/docs/headers generated alongside it; the fix belongs in the spec, so it propagates to all artifacts and persists — generated files are outputs, never edited.

3. Concept — the spec is the source of truth; generated files are outputs

Production RAL is a pipeline from one spec to many artifacts:

The spec is the single source of truth. A machine-readable register specification (IP-XACT / RALF / CSRSpec, 13.2/13.3) is the authoritative description of the registers — addresses, fields, access policies, reset values.
Multiple artifacts are generated from it. A generator produces, from the same spec: the UVM register model, often the RTL register block, the documentation, and firmware/C headers. Because they share one source, they are consistent by construction — the model matches the RTL matches the docs matches the software.
Generated files are outputs — never hand-edit. The model (and the other artifacts) are outputs of the generator. Hand-editing an output is a category error: it is overwritten on the next regeneration, and it diverges from the spec (and thus from the other artifacts) until then.
Fix the spec, regenerate. The correct way to change a generated model is to change the spec and regenerate — so the change propagates to all artifacts consistently and survives future regenerations.

Here is the pipeline, with the hand-edit anti-pattern:

Figure 1 — production RAL is a pipeline from ONE spec to MANY artifacts. The machine-readable spec (IP-XACT/RALF/CSRSpec) is the SINGLE SOURCE OF TRUTH; a generator produces the UVM register model, (often) the RTL register block, the documentation, and firmware/C headers — all consistent because they share one source. The MASTER RULE: generated files are OUTPUTS, never hand-edited. The anti-pattern (bottom): hand-editing the generated model — the edit is OVERWRITTEN on the next regen (lost) and, until then, the model DIVERGES from the spec and from the RTL/docs/headers. The fix belongs in the SPEC: change it, regenerate, and the fix propagates to all artifacts and survives.

4. Mental Model — the model is compiled output; you edit the source, not the binary

Mental Model — a generated model is like a compiled binary; editing it is editing the wrong thing, and it will be rebuilt from source

A generated register model is compiled output from the spec 'source code.' Editing the generated model is like patching a binary instead of the source: your patch is lost the next time it is rebuilt, and until then the binary disagrees with the source everyone else builds from.

The most useful way to think about a generated register model is by analogy to compilation: the spec is the source code, the generator is the compiler, and the model (along with the RTL, docs, and headers) is the compiled output. Nobody edits a compiled binary to fix a bug — you edit the source and recompile, because (a) the binary will be rebuilt from source and your edit overwritten, and (b) editing the binary makes it disagree with the source that everyone else builds from. Exactly the same logic applies to a generated model. Hand-editing it is 'patching the binary': your edit survives only until the next regeneration, which will overwrite it from the spec — so the fix is ephemeral. And while your edit is in place, the model disagrees with the spec, and therefore with the RTL and C headers that were also compiled from that spec — so you have created a divergence between the model (says RW) and the hardware/software (say RO). The correct move is the one you would make for a compiled bug: fix the source (the spec) and recompile (regenerate). Then the fix flows to every artifact at once — model, RTL, docs, headers all update together and stay mutually consistent — and it persists, because it is now in the source everyone builds from. This mental model also explains why production uses generation at all: the whole point is one source, many consistent outputs, so that the model can never silently disagree with the RTL or the driver headers — a guarantee that only holds if nobody edits the outputs. Hand-editing an output breaks the single guarantee generation exists to provide.

Two habits:

Treat the generated model as compiled output. Never hand-edit it; the fix goes in the spec (the source), then regenerate — the edit to an output is lost on regen and diverges until then.
Fix the spec so it propagates to all artifacts. A spec change updates model, RTL, docs, and headers together and consistently — which is the entire reason to generate.

5. Working Example — fixing in the spec, not the generated model

Change the spec (source of truth) and regenerate, rather than editing the generated output:

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Snippet

// A GENERATED register model file typically carries a DO-NOT-EDIT banner — it is an OUTPUT:
// =============================================================================
//  GENERATED FILE — DO NOT EDIT. Generated from regs.ipxact by ralgen.
//  Edit the SPEC (regs.ipxact) and regenerate; hand-edits are overwritten.
// =============================================================================
class my_reg_block extends uvm_reg_block; /* ...generated content... */ endclass

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Snippet

# THE FIX belongs in the SPEC (here IP-XACT, 13.2), not the generated model.
# Wrong policy found: 'status.mode' generated as RO but should be RW.
#   1. Edit the SPEC: set status.mode access = read-write.
#   2. Regenerate: ralgen regs.ipxact -> UVM model + RTL + docs + C headers all updated together.
#   3. The fix now propagates to ALL artifacts consistently AND survives future regenerations.
# (Editing the generated .sv would revert on the next regen and diverge from the spec-driven RTL/headers.)

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Snippet

// Because ALL artifacts come from ONE spec, they are consistent BY CONSTRUCTION:
//   UVM model access policy == RTL register behaviour == doc table == C-header #define
// A spec change keeps them aligned; a hand-edit to any single OUTPUT breaks that alignment.

Fixing the spec and regenerating updates every artifact together and persists; editing the generated model — the bug of the next section — reverts on regen and diverges until then.

6. Debugging Session — a hand-edited generated model that reverts and diverges

A fix hand-edited into the generated register model is overwritten on the next regeneration and, until then, diverges from the spec-driven RTL and headers

FIX THE SPEC, NOT THE OUTPUT

Buggy Code

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Snippet

// A wrong access policy is 'fixed' by editing the GENERATED model file directly:
// (in the generated my_reg_block.sv — an OUTPUT, marked DO-NOT-EDIT)
mode.configure(this, 1, 0, "RW", 0, 1'b0, 1, 1, 0);   // hand-changed from "RO" to "RW" in the OUTPUT
// BUG: this edits a GENERATED file. It will be OVERWRITTEN on the next regen from the spec,
// and meanwhile the MODEL says RW while the SPEC (and RTL + C headers) still say RO -> DIVERGENCE.

Symptom

Two symptoms, one after the other. Immediately: the tests pass (the hand-edit made the model say RW), so the fix seems to work. Then, after the next regeneration (a nightly flow, another engineer's regen, a clean build), the model file is overwritten from the spec — the RW edit is gone, back to RO — and the tests fail again, with the baffling 'but I fixed this' feeling. And even before the revert, a subtler symptom lurks: the model says RW while the RTL (generated from the spec) still enforces RO, so the model and hardware disagree — a divergence that could itself cause mismatches. Nothing about editing the file warned that it was a generated output whose edits are transient and divergent.

Root Cause

The register model is a generated output of a spec-driven pipeline, and the engineer edited the output instead of the source. Two consequences follow, both inherent to generation. First, the edit is overwritten: the model is regenerated from the spec on every regen, and regeneration replaces the file wholesale, so any hand-edit is lost the next time the generator runs — the fix is ephemeral by construction. Second, the edit diverges: while it is in place, the model reflects the hand-edit (RW) but the spec still says RO, and since the RTL, docs, and C headers are also generated from that same spec, they all still say RO — so the hand-edited model disagrees with the hardware and software it is meant to describe. The underlying error is a category confusion: treating a generated artifact as hand-maintained source. The single guarantee that generation provides — that the model, RTL, docs, and headers are mutually consistent because they share one source — is broken the instant an output is edited, because the output no longer derives from the shared source. The 'fix' was placed in the wrong layer entirely: it addressed a symptom in an output rather than the cause in the source.

Fix

Put the fix in the spec: determine whether the correct policy is RO or RW (a spec question), edit the spec accordingly, and regenerate — so the correct policy propagates to the model, RTL, docs, and headers together, stays mutually consistent, and survives future regenerations. Never edit a generated file (they typically carry a DO-NOT-EDIT banner precisely for this reason); if the generator's output is wrong in a way the spec cannot express, fix the generator or the spec format, not the output. The rule the bug teaches: in production RAL the register model is a generated output — hand-editing it means the fix is overwritten on the next regeneration and diverges from the spec-driven RTL/docs/headers until then; the fix belongs in the spec, so it propagates to all artifacts and persists. The single most important production-RAL habit is: the spec is the source of truth; generated files are outputs, never edited — when a generated model is wrong, fix the source, not the output.

7. Common Mistakes

Hand-editing the generated model. It is overwritten on the next regeneration and diverges from the spec/RTL/headers until then — fix the spec and regenerate.
Treating a generated file as hand-maintained source. A category error — generated files are outputs; the spec is the source of truth.
Ignoring the DO-NOT-EDIT banner. It marks a generated output precisely because edits are transient and divergent.
Fixing a symptom in one output instead of the shared source. A spec fix propagates to all artifacts consistently; an output edit fixes one and breaks alignment.
Not regenerating after a spec change. The artifacts only update when you regenerate — a spec change alone does not touch the outputs until the generator runs.

8. Industry Best Practices

Treat the spec as the single source of truth. Addresses, fields, policies, resets live in the spec (IP-XACT/RALF/CSRSpec) — the authoritative description.
Never hand-edit generated files. Model, RTL, docs, headers are outputs — fix the spec and regenerate so changes propagate and persist.
Regenerate to keep artifacts consistent. One spec change updates model, RTL, docs, and firmware headers together, by construction.
Fix the generator/spec-format for output-only issues. If the output is wrong in a way the spec cannot express, the fix is in the generator or format, not the output.
Keep generated files out of hand-maintenance. Mark them DO-NOT-EDIT, ideally regenerate in CI, so no one treats an output as source.

9. Interview / Review Questions

10. Key Takeaways

In production, the register model is generated, not hand-written: a machine-readable spec (IP-XACT/RALF/CSRSpec) is the single source of truth, and a generator produces the UVM model, RTL register block, docs, and firmware/C headers from it.
Because all artifacts share one source, they are consistent by construction — the model matches the RTL matches the docs matches the software.
The master discipline: generated files are outputs, never hand-edited — you edit the spec and regenerate, like editing source and recompiling rather than patching a binary.
The signature bug is hand-editing the generated model: the edit is overwritten on the next regeneration (fix lost) and, until then, the model diverges from the spec and from the RTL/docs/headers generated alongside it.
Fix the spec, regenerate — so the fix propagates to all artifacts consistently and survives; when a generated model is wrong, fix the source (spec), or for output-only issues the generator/format — never the output.