Two parts, one dependency chain
Part I is a complete Tcl education that stands on its own — the execution model, expr, strings, lists, dicts and arrays, procedures, scope, files, regex and the error model — with no EDA tool and no VLSI knowledge assumed. Part II builds on it and never re-teaches it.
Standard Tcl, kept separate from tool commands
get_cells, create_clock and report_timing are taught as commands a vendor adds to its own interpreter, not as Tcl — named as such before any of them appears, with the portability limits stated rather than implied.
Script → constrain → sign-off
From the Tcl-as-command mental model to SDC constraint generators, multi-corner STA drivers, violation extractors, and PD report collectors — the full Tcl engineering loop every synthesis / STA / PD engineer owns.
Your Learning Roadmap
258 chapters · 30 modules — two parts — Tcl taught from zero, then the Tcl a synthesis, STA, physical-design or verification engineer uses inside an EDA tool.
Part I — Tcl Basics & Fundamentals
Tcl taught from zero with no EDA tool and no VLSI knowledge required: running your first script, the command-and-substitution execution model that explains everything else, values and expr, operators, strings, lists, dictionaries and arrays, conditions, iteration, procedures, scope and namespaces, files and paths, regular expressions, the error model, and assembling a script someone else can run.
Part II — Tcl for VLSI & EDA Engineering
The Part I foundation applied to semiconductor work, and never re-teaching it: how a tool embeds Tcl and where vendors diverge, collections and design objects, querying a design database, SDC as Tcl, synthesis and STA automation, physical design, simulator and verification Tcl, report and log processing, multi-corner multi-mode flows, reusable flow infrastructure, the hand-off to Bash / Make / Python, debugging a production flow, and the scripts engineers actually ship.
