AMBA AXI · Module 15

Ready/Valid Pipelining

Chain registered VALID/READY handshakes into a multi-stage pipeline without losing data or throughput — how backpressure propagates upstream stage-by-stage, why each stage needs a skid (not a bare register), the enable rule that gates every stage, and how to add compute stages while keeping the handshake intact.

A skid buffer registers one handshake stage. Real datapaths need many stages — an AXI path might register a port boundary, then an address decode, then an arbiter, then an alignment/conversion step, each adding a cycle of latency for timing. Chaining them correctly is ready/valid pipelining: a sequence of stages, each driving the next with a VALID/READY handshake, where data flows forward and backpressure propagates backward stage-by-stage, with no data lost and full one-beat-per-cycle throughput preserved when nothing stalls. Get the per-stage rule wrong and you either drop beats under backpressure or bubble the pipeline. This chapter builds the multi-stage pattern on top of the skid buffer, derives the universal per-stage enable rule, and shows how to interleave compute with the handshake.

1. The Pipeline Structure

A ready/valid pipeline is a chain of stages connected by handshakes: stage k's output (valid_k, data_k) is stage k+1's input, and stage k+1's ready feeds back to stage k. Data moves forward when a stage's output handshake completes; backpressure (a downstream ready going low) ripples backward as each stage in turn fills and deasserts its own ready.

Figure 1 — a multi-stage ready/valid pipeline. Each stage hands off to the next with a VALID/READY handshake. Data (valid/payload) flows left-to-right; READY (backpressure) flows right-to-left. A stall at the sink propagates upstream one stage per cycle as each stage fills, until it reaches the source. Each inter-stage boundary is a registered handshake (a skid buffer) so the whole path is timing-closed.

2. The Universal Stage Enable Rule

Every pipeline stage obeys one rule. A stage advances (latches new data from upstream, or shifts its data downstream) only when it is either empty or its output is being consumed this cycle. Expressed with the handshake signals, a stage's register enable is:

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Snippet

// Stage k holds: valid_k, data_k. Upstream: valid_in/ready_out. Downstream: ready_k
// The stage can accept/advance when it's empty or its output is leaving:
assign ready_out = !valid_k || ready_k;          // upstream-facing READY
wire   advance   = ready_out;                    // enable for this stage's register
 
always_ff @(posedge clk) begin
  if (!rstn)            valid_k <= 1'b0;
  else if (advance) begin
    valid_k <= valid_in;                         // take new beat (or go empty)
    if (valid_in) data_k <= data_in;             // payload only when valid
  end
end

The crucial term is ready_out = !valid_k || ready_k: a stage presents READY upstream when it has no beat (!valid_k) or when its current beat is being taken downstream (ready_k). This single expression is what makes backpressure propagate exactly one stage per cycle and guarantees no overwrite of an unconsumed beat.

Figure 2 — the per-stage enable logic. A stage's upstream-facing READY is asserted when the stage is empty (!valid) OR its output is being consumed (downstream ready). That same condition enables the stage's register to advance — taking a new beat from upstream. The combinational READY chain (ready_k feeding ready_out) is exactly what a skid buffer breaks when you need it registered.

3. Bare Registers vs. Skid Stages

The enable rule above describes a bare pipeline register (one slot per stage): correct, full-throughput, but it leaves ready_out combinational off ready_k — so the READY path ripples through the entire pipeline in one cycle, which defeats the timing purpose. Two options:

Skid stage per boundary. Replace each bare register with a skid buffer (Chapter 15.5): both VALID and READY are registered at every boundary, so no combinational READY path spans more than one stage. Full throughput, fully timing-closed, at the cost of two registers per stage and one cycle latency each.
Periodic skid insertion. Use bare registers for most stages and insert a skid buffer every few stages to chop the combinational READY chain into bounded segments — a pragmatic area/timing trade when the READY path through a few bare stages still meets timing.

The decision is the same as for a single stage: register the READY path (via skid) exactly where it would otherwise be the critical path; use bare registers where it wouldn't.

Figure 3 — bare register vs. skid stage. A bare pipeline register registers only VALID/data, leaving READY to ripple combinationally through every stage — the READY critical path grows with pipeline depth. A skid stage registers both directions, bounding the READY path to one stage. Choose skid where the cumulative READY path fails timing; bare registers are cheaper where it doesn't.

4. The Timing: Backpressure Propagation

The waveform shows a three-stage pipeline streaming one beat per cycle, then the sink stalls. Backpressure climbs the pipeline one stage per cycle — each stage holds its beat as its downstream ready drops — until the source is held. When the sink resumes, the pipeline drains forward and full-rate streaming returns. No beat is lost; the only cost is the stall depth in latency.

Backpressure climbing a 3-stage ready/valid pipeline

10 cycles

Figure 4 — backpressure propagating up a 3-stage pipeline. Beats stream one per cycle until the sink drops ready_3 (cycle 4). The stall climbs upstream: stage 3 fills and drops ready_2, then stage 2 fills and drops ready_1, then the source is held — one stage per cycle. When the sink resumes (cycle 6), beats advance again and the pipeline returns to full rate. Each stage holds its payload stable while back-pressured; nothing is dropped.

5. Common Misconceptions

Myths to unlearn

"You can pipeline a handshake with plain registers and ignore READY." Plain forward registers without the enable rule overwrite unconsumed beats under backpressure — data loss. Every stage must gate its register on the !valid || ready enable.
"Bare pipeline registers close timing." They register VALID/data but leave READY combinational across the whole pipeline, so the READY path grows with depth and often becomes the critical path. To register the backward path you need skid stages.
"More pipeline stages reduce throughput." Stages add latency, not throughput loss — a correctly built ready/valid pipeline still passes one beat per cycle in steady state regardless of depth. Throughput only drops if a stage bubbles (a design bug) or the sink stalls.
"Backpressure is instantaneous across the pipeline." With registered stages it propagates one stage per cycle upstream; the source may keep sending for a few cycles after the sink stalls, which is exactly why each stage needs its own holding slot (skid) and why deep pipelines need the source to tolerate that latency.
"A stage can drop its valid whenever it likes." Once a stage asserts valid it must hold it (and stable payload) until its downstream takes the beat — the enable rule preserves this; violating it loses or corrupts beats.
"You can insert a compute block in the path without touching the handshake." Combinational compute is fine inside a stage, but a registered (multi-cycle) compute block must participate in the handshake — assert valid only when its result is ready and accept input only when it can — or it breaks flow control.

6. Debugging Insight

🔍 Debugging insight — pipeline flow-control bugs are lost beats, bubbles, or a too-long READY path

Multi-stage ready/valid bugs localize cleanly:

Beats lost under backpressure. A stage overwrites an unconsumed beat — its register enable isn't gated by !valid || ready. Find the stage whose enable ignores downstream ready; that's where the beat vanishes.
Throughput drops to 1-in-2 (or worse). A stage bubbles — usually it deasserts ready whenever it holds a beat (treating "occupied" as "full") instead of only when it can't pass the beat on. Re-derive ready_out = !valid || ready_k.
Timing fails on a READY path. The combinational READY chain spans too many bare-register stages. Insert a skid buffer to chop the chain; locate the longest ready → ready → ready run in the path report.
Backpressure doesn't reach the source (source keeps sending, overflow). A stage's ready_out isn't actually fed from the next stage's fill state, so the stall never climbs. Trace the ready chain end-to-end.
Payload corrupted at a stage during a stall. The data register updates while the stage is back-pressured — its enable fires when it shouldn't. The data enable must match the valid enable (advance only).
A multi-cycle compute stage desyncs. Its internal latency isn't reflected in valid/ready — it asserts valid before the result is ready or accepts input mid-computation. Make the compute block a proper handshake participant.

The two signature failures are lost-beat (enable ignores ready) and bubble (ready too conservative) — identical to the skid buffer's signature bugs, because each stage is a skid/register obeying the same rule.

7. Verification Insight

✅ Verification insight — end-to-end conservation plus stall storms across the whole pipeline

A ready/valid pipeline is verified end-to-end as a flow-controlled channel. Always-on assertions: per-stage payload stability (data stable while valid && !ready); valid never drops with a beat pending; and the end-to-end conservation/ordering property — every beat injected at the source emerges exactly once at the sink, in order, with the correct fixed latency when un-stalled. Directed/random tests: a stall storm — drive continuous input at the source and toggle the sink ready in every pattern (single-cycle, multi-cycle, alternating, long holds), confirming no beat is lost, no bubble appears when the pipeline isn't stalled, and ordering is preserved; then the symmetric sparse-input/always-ready case. Verify backpressure depth: stall the sink and confirm the stall reaches the source after exactly N cycles for an N-stage pipeline (no sooner, no later). For pipelines with compute stages, check the data transform per beat against a reference model, with stalls injected mid-compute. Formal scales well for the flow-control skeleton: prove conservation, ordering, and no-overflow with the payload abstracted, since the per-stage state is tiny; the data transform is verified separately. Coverage: each stage reaching full/empty, backpressure reaching every depth, and simultaneous stalls at multiple stages. The highest-value test is the stall storm with end-to-end conservation — it catches both lost-beat and bubble bugs at every stage at once, which is why it's the standard sign-off for any handshaked pipeline. Because each stage reuses the verified skid/enable primitive, the pipeline's correctness reduces to the per-stage rule plus the end-to-end conservation proof.

8. Interview Questions

9. Summary

Ready/valid pipelining chains registered handshake stages so data flows forward and backpressure propagates backward one stage per cycle, with no loss and full throughput. Every stage obeys one universal rule: it advances (latches a new beat) only when empty or its output is being consumed — ready_out = !valid || ready_downstream, which is also the register enable. That single invariant guarantees no overwrite of a pending beat (no loss) and acceptance of a replacement exactly when the current beat leaves (no bubble), so a chain of such stages is a lossless, order-preserving, one-beat-per-cycle channel of arbitrary depth.

A bare pipeline register registers only VALID/data, leaving the READY path combinational across the whole pipeline; to register the backward path and bound the READY critical path you use skid stages (Chapter 15.5) at the boundaries that need them — full skid where the READY path fails timing, bare registers (or periodic skid insertion) where it doesn't. Adding stages adds latency, not throughput loss, and backpressure's one-stage-per-cycle climb means deep pipelines have deep stall latency the source must tolerate. Compute blocks integrate by becoming handshake participants (output valid only when ready, input ready only when able, freeze under backpressure). Verification is a stall storm plus end-to-end conservation/ordering — the standard sign-off for any handshaked pipeline. Next, we add real buffering with FIFOs to decouple producer and consumer rates.

10. What Comes Next

You can now pipeline a handshake to any depth; next we add genuine buffering to decouple rates:

15.7 — FIFO-Based Buffering (coming next) — using FIFOs to decouple producer and consumer rates on AXI, absorbing bursts and bridging rate mismatches beyond what a two-entry skid can.

Previous: 15.5 — The Skid Buffer. Related: 3.1 — The VALID/READY Handshake for the per-stage contract, 3.3 — Backpressure & Stalls for the stall propagation, and 13.2 — Latency Analysis for how pipeline depth shows up as latency.