AMBA AXI · Module 5

Read Latency

What AXI read latency is and where it comes from — request-to-first-data, the round-trip contributors (routing, subordinate access, return), latency vs throughput, and how outstanding reads hide it.

A read takes time, and that time has a name and a structure worth understanding precisely. Read latency is the delay from issuing the address to the first data beat coming back — and it's distinct from throughput, which is how fast beats stream once they start. This chapter defines read latency exactly, decomposes it into its round-trip contributors (routing, the subordinate's own access time, the return path), separates latency from throughput on a waveform, and shows the one lever that hides it: outstanding reads. Read latency is where the performance modules (8, 13) begin, and this is the chapter that makes it concrete on the read path.

1. Defining Read Latency

Read latency is the time from the read being launched (the AR handshake) to the first R data beat arriving. It is a per-transaction property — one number per read — measuring the round trip from "I asked" to "I got the first answer."

Read latency = cycles from ARVALID && ARREADY to the first RVALID && RREADY.

It is emphatically not the same as the whole read's duration. The total time to receive an N-beat read is roughly latency + N beats of throughput: you pay the latency once to get the first beat, then the remaining beats stream at the channel's throughput (Chapter 3.4). So a 64-beat read isn't 64× the latency — it's one latency plus 63 more beats. Separating these two is the foundation of read performance reasoning.

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Snippet

// Conceptual — measure read latency: AR accepted → first R beat of that read.
if (arvalid && arready)              t_launch[arid] = now();   // read issued
if (rvalid && rready && first_of[rid])
  read_latency[rid] = now() - t_launch[rid];                   // request → first data

2. The Round-Trip Contributors

Read latency is a round trip, and naming its segments is what lets you attribute a slow read. From the AR handshake to the first R beat, the request and its answer traverse:

AR acceptance — the address handshake itself (often 1 cycle, more if the target backpressures ARREADY).
Interconnect forward path — decode (which subordinate owns the address), arbitration (if other masters contend), and the routing/pipeline stages to the target. Each interconnect hop adds cycles.
Subordinate access time — the target actually fetching the data. This is usually the dominant term (below).
Return path — the first R beat travels back through the interconnect (and any pipeline/CDC stages) to the manager.

Figure 1 — read latency as a round trip, time downward. The AR handshake launches the read; the interconnect decodes/arbitrates and forwards it; the subordinate fetches (usually the largest term); the first R beat returns through the interconnect to the manager. Latency is the sum of all these segments — request to first data.

3. The Dominant Term — Subordinate Access

Across these segments, the subordinate's own access time usually dominates, and it varies enormously by target:

On-chip SRAM / registers: a few cycles — fast, deterministic.
DRAM (through a controller): tens of cycles, and variable — a row already open is fast; a row miss (precharge + activate) is much slower; refresh and bank conflicts add more.
A bridged / off-chip / NoC-distant target: more still, plus any clock-domain-crossing penalty.

So "read latency" is mostly "how far away and how slow is the thing I'm reading." Two reads on the same bus can have very different latencies purely because one hit SRAM and the other hit a closed DRAM row. The interconnect terms (decode, arbitration, hops) add to it — and contention makes them variable: under heavy traffic, arbitration delay at a shared port can dominate even a fast target.

Figure 2 — what dominates read latency. The interconnect adds decode/arbitration/hop cycles (variable under contention), but the subordinate's access time is usually the largest and most variable term — a few cycles for SRAM, tens for DRAM (and far more on a row miss). 'How far and how slow is the target' is most of the latency.

4. Latency vs Throughput

The two are different axes, and a waveform makes the distinction unmistakable: latency is the gap before the first beat; throughput is the rate of the beats once they arrive.

Read latency (the gap) vs throughput (the stream)

11 cycles

Figure 3 — latency vs throughput. The AR is accepted at cycle 2, but the first R beat doesn't arrive until cycle 6 — that gap (cycles 2→6) is the read latency. Once data starts, D0–D3 stream back-to-back at full throughput (a beat per cycle), with RLAST on the last. Latency is paid once to get the first beat; throughput governs the rest.

This is why bursts are efficient (Chapter 1.6): one latency amortizes over many beats. A single-beat read pays the full latency for one beat of data; a long burst pays the same latency once and then streams — so the effective per-byte cost of latency drops as the burst lengthens. Latency hurts most on short, scattered reads.

5. Hiding Latency — Outstanding Reads

Latency is paid per transaction, but it doesn't have to be paid serially. Because AR and R are decoupled (Chapter 2.4), a manager can issue the next read's AR while earlier reads are still in flight — so multiple reads' latencies overlap instead of stacking. The first read's data is still on its way when the second, third, and fourth are already launched; their latencies run concurrently, and data streams back in a near-continuous flow.

Figure 4 — outstanding reads hide latency. Issuing reads serially pays each latency end-to-end (slow, gaps between every read). Issuing them outstanding — launching the next AR before the previous data returns — overlaps the latencies, so after the first read's latency the data streams back nearly continuously. Same per-read latency; far higher delivered bandwidth.

This is the technique for tolerating memory latency, and it's why AXI's outstanding/out-of-order machinery exists (Module 8). The latency of any single read doesn't shrink — but the system stops waiting on it. (Depth tuning — how many outstanding reads you need to fully hide a given latency — is Module 13.)

6. Common Misconceptions

Myths to unlearn

"Read latency is the whole read's duration." No — it's request → first data. The total is roughly latency + the remaining beats at throughput; a long burst pays the latency once, not per beat.
"Latency and throughput are the same thing." Different axes: latency is the gap before the first beat (per transaction); throughput is beats-per-cycle once data flows. You can have low latency and low throughput, or high latency and high throughput.
"Latency is fixed for a bus." It's highly variable — dominated by the target's access time (SRAM few cycles, DRAM tens, row miss more) and by contention (arbitration delay under load). Two reads on the same bus can differ greatly.
"You reduce latency by making the bus faster." The dominant term is usually the subordinate's access time, not bus speed. The system-level fix for latency is to hide it with outstanding reads, not to shave bus cycles.
"Outstanding reads make each read faster." They don't reduce any single read's latency — they overlap multiple reads' latencies so the system isn't stalled waiting. Per-read latency is unchanged; delivered bandwidth rises.

7. Debugging Insight

🔍 Debugging insight — measure the gap, then attribute it

When reads feel slow, quantify and localize the latency rather than guessing:

Measure it. On a capture, find the AR handshake and the first R beat of that read; the cycle gap is the latency. Do this for several reads — a consistent gap points to fixed path/access cost; a variable gap points to contention or DRAM row effects.
Attribute the segments. If you can probe the interconnect and subordinate interfaces: how long until the request reaches the subordinate (forward path + arbitration)? How long until the subordinate produces the first beat (access time)? How long to return? The biggest segment is your target for improvement.
Latency high but throughput fine? The data streams well once it starts — so the problem is the front of the read (access time / routing), and the cure is usually more outstanding reads to hide it, or a faster/closer target — not touching the data path.
Latency variable and load-dependent? Suspect arbitration contention at a shared interconnect port (other masters competing) or DRAM row misses — both make latency spike under traffic.

The discipline: latency is a measurable gap with named contributors. Measure the gap, attribute it to a segment, then decide between hiding it (outstanding) and reducing it (closer/faster target, less contention).

8. Verification Insight

✅ Verification insight — model and measure latency, don't just check data

Functional checks confirm a read returns the right data; they say nothing about how long it took — so latency is a separate verification concern. Two pieces. Performance monitoring: a passive monitor timestamps each read's AR handshake and first R beat to report per-read latency (and flag regressions). Latency modeling in the responder: the slave/responder agent must inject realistic, variable read latency — random delay before the first R beat, modeling fast (SRAM-like) and slow (DRAM-row-miss-like) targets — so the master is verified to tolerate a wide range of first-beat delays, not just an instantaneous responder.

This variable-latency stimulus matters for correctness, not just performance: a master that secretly assumes data returns quickly (under-sized buffers, a too-short timeout, a fragile outstanding-read tracker) only breaks when the responder is slow. Combine it with multiple outstanding reads and out-of-order returns (5.2) so the latency-hiding logic itself is exercised. Coverage wants a spread of first-beat latencies and outstanding depths. Mechanics in Module 16.

9. Interview Questions

10. Summary

Read latency is the round-trip delay from the AR handshake to the first R data beat — a per-transaction number, distinct from throughput (the rate of beats once they flow). Its contributors are the forward path (AR acceptance, interconnect decode/arbitration/hops), the subordinate access time (usually the dominant and most variable term — a few cycles for SRAM, tens for DRAM, more on a row miss), and the return path. Because latency is paid once per transaction, bursts amortize it (one latency, many beats), so latency hurts most on short, scattered reads.

Latency can't easily be made small — it's mostly the target's access time and any contention — so the system-level answer is to hide it with outstanding reads: decoupled AR/R let a manager overlap many reads' latencies, turning serial waits into a near-continuous stream without changing any single read's latency. Debug by measuring the gap and attributing it to a segment; verify by modeling variable latency in the responder (a correctness check, not just performance) alongside outstanding/out-of-order returns. Next: how read data from different transactions could be interleaved (AXI3) and why AXI4 removed it.

11. What Comes Next

You can reason about a read's timing; next, how multiple reads' data shares the R channel:

5.5 — Read Data Interleaving (coming next) — interleaving by ID in AXI3 and its removal in AXI4.
5.6 — Read Transaction Waveforms (coming soon) — annotated end-to-end read waveforms (single, burst, multi-ID).

Previous: 5.3 — RLAST & RRESP. For the broader protocol catalog, see the AMBA family overview doc.