AMBA AXI · Module 12

Decoder & Address Map

How the AXI interconnect decoder maps AxADDR to a subordinate port — the address map structure, the decode process, unmapped-address DECERR, region constraints (no overlaps/holes), and decode timing/latency.

The interconnect's routing job (Chapter 12.1) is implemented by the decoder and the address map. The address map assigns each subordinate a region of the global address space; the decoder compares each transaction's AxADDR against that map to select the target subordinate port. This is the mechanism that turns an address into a destination — and getting the map right (no overlaps, no unexpected holes, correct sizes) is foundational to a working SoC. This chapter covers the address-map structure, the decode process, unmapped-address handling (DECERR), the region constraints, and decode timing.

1. The Address Map

The address map is the interconnect's table of which address range belongs to which subordinate port. Each subordinate occupies a region defined by a base address and a size (e.g., DRAM at 0x8000_0000–0xFFFF_FFFF, a peripheral block at 0x4000_0000–0x4000_FFFF). Together the regions partition (part of) the global address space among the subordinates.

The map is the contract for the whole system: software, masters, and the interconnect must agree on it. It defines where each subordinate "lives" so that an AxADDR unambiguously identifies one destination. Regions are typically aligned and power-of-two sized so the decoder can select a port by comparing just the high address bits (cheap, fast hardware) rather than a full magnitude compare.

Figure 1 — the address map. Each subordinate occupies a base+size region of the global address space (DRAM, peripherals, accelerator, …). The map partitions the address space so any AxADDR identifies one subordinate. Regions are typically aligned/power-of-two so the decoder selects a port from the high address bits.

2. The Decode Process

When a transaction arrives, the decoder:

Takes its AxADDR.
Determines which region the address falls in (typically by comparing high address bits against each region's base/mask).
Routes the transaction to that region's subordinate port (and remembers the mapping so the response routes back, via the extended ID).

If the address matches no region (a hole / unmapped address), the decoder routes it to a default slave that returns DECERR — the protocol's "no subordinate here" response (Chapter 6.8). The decoder may also drive AxREGION (Chapter 6.5) so a subordinate exposing multiple regions knows which one without re-decoding the address itself.

Because the 4 KB boundary rule (Chapter 7.6) guarantees a burst stays within one region, the decoder only needs to decode the single start address — it can route the whole burst on that one decision, never having to split a transaction mid-flight. This is exactly why the 4 KB rule exists: it keeps decode simple and single-shot.

decode-timing — address decode to subordinate port select

5 cycles

Figure 2 — decode-timing: AxADDR is presented, the decoder compares it against the address map (often registered, adding a cycle of latency), selects the target subordinate port (S2 here), and routes the transaction. Because the 4 KB rule confines a burst to one region, the single start-address decode routes the whole burst.

3. Region Constraints — No Overlaps, Defined Holes

A valid address map has hard constraints:

No overlapping regions. Two subordinates' regions must not overlap — an address in the overlap would be ambiguous (which subordinate?). Overlapping regions are an illegal/broken map.
Holes decode to DECERR. Address ranges assigned to no subordinate are unmapped; accesses to them return DECERR from the default slave. Holes are legal (not all of the space is populated) but accessing one is an error the system should handle.
Alignment/size for clean decode. Regions sized to powers of two and aligned to their size let the decoder use simple high-bit masking, avoiding expensive full-range compares.

Two related subtleties: aliasing — if the decoder compares only some address bits, an address can alias into a region (sometimes intentional — mirroring a small subordinate across a larger window; sometimes a decode bug); and security — the decoder can incorporate AxPROT (Chapter 6.5) so a secure-only region rejects non-secure accesses at decode time (a TrustZone check in the routing path).

Figure 3 — address-map constraints. Regions must not overlap (an overlap address is ambiguous — illegal map). Unmapped holes are legal but accesses to them return DECERR via the default slave. Power-of-two aligned regions enable cheap high-bit decode. Watch for aliasing (partial-bit decode mirroring a region) and security checks (AxPROT at decode for secure regions).

4. Decode Timing

The decode is on the address path, so it costs latency and affects timing closure:

A combinational decoder produces the port select in the same cycle the address arrives — lowest latency, but the compare logic is in the critical path (can limit clock frequency on a large map).
A registered/pipelined decoder adds a cycle (or more) of latency but breaks the critical path, helping frequency on big interconnects.

So decode is a latency-vs-frequency trade, like any pipelining choice. A large address map (many regions) means more comparison logic; pipelining it keeps the interconnect fast at the cost of a cycle on every transaction's address phase. Since the address phase is amortized over a burst (4 KB-confined), a cycle of decode latency is usually a fine trade for the frequency it buys. The decode latency adds to the overall transaction latency, which feeds back into the outstanding-depth needed to hide it (Chapters 8.1/8.5).

Figure 4 — decode timing trade-off. A combinational decoder selects the port in-cycle (lowest latency, but the compare is in the critical path, limiting frequency on large maps). A registered/pipelined decoder adds a cycle but breaks the critical path (higher frequency). Decode latency adds to transaction latency, feeding the outstanding depth needed to hide it.

5. Common Misconceptions

Myths to unlearn

"The interconnect routes by ID." No — it routes by address decode (AxADDR → region → port). IDs handle response matching/return-routing, not slave selection.
"Overlapping regions are fine if priority resolves them." Overlaps make an address ambiguous — a broken map. Regions must be disjoint; don't rely on priority to paper over an overlap.
"Every address maps to a subordinate." Not necessarily — holes (unmapped ranges) are legal, and accesses to them return DECERR from the default slave. The map need not be fully populated.
"The decoder must compare the full address." Usually not — power-of-two aligned regions let it decode on high bits only (cheap). Full magnitude compares are avoided by design.
"Decode is free." It adds latency to the address path and can be a critical-path limiter; large maps are often pipelined (adding a cycle) to keep frequency.
"The decoder must re-decode every burst beat." No — the 4 KB rule confines a burst to one region, so a single start-address decode routes the whole burst.

6. Debugging Insight

🔍 Debugging insight — wrong-target, DECERR, and decode-timing issues

Decode/address-map bugs are routing problems with clear signatures:

A transaction reaches the wrong subordinate? The address map is wrong — a region's base/size is mis-set, or two regions overlap (ambiguous). Check the map against the intended layout and the actual AxADDR.
An access returns DECERR unexpectedly? The address is unmapped — a hole, or the region's base/size doesn't cover it, or the master is computing the wrong address. Compare the address to the map; the gap is the hole.
An access should DECERR but reaches a slave? Aliasing — partial-bit decode mirrors a small region across a larger window, so an out-of-range address aliases in. Check how many address bits the decoder compares.
Two subordinates respond / contention to one address? Overlapping regions — the map is illegal. Make regions disjoint.
Interconnect failing timing closure? The combinational decoder on a large map is in the critical path — pipeline/register it (accepting a cycle of latency).
A secure region accessible by non-secure masters? The decode isn't checking AxPROT for that region — add the security check in the decode path.

The triage: wrong-slave → map base/size or overlap; unexpected DECERR → unmapped/wrong address; missing DECERR → aliasing; timing → combinational decode on a big map; security leak → missing AxPROT check. All localize to the address map or the decode logic.

7. Verification Insight

✅ Verification insight — exercise the whole map, holes, and boundaries

Address-decode verification must cover the entire address map and its edges. For every region: accesses route to the correct subordinate (a directed access per region, plus the region's base and top addresses — boundary decode). For holes: unmapped addresses return DECERR from the default slave. For boundaries: addresses at region edges decode to the right region (off-by-one boundary bugs are common). Assert no overlaps exist (a static map check) and that aliasing, if intended, behaves as specified (and if not intended, doesn't occur). If the decode incorporates AxPROT/security, verify secure regions reject non-secure accesses at decode.

Coverage should include: one access to each region; each region's first and last address; unmapped/hole addresses (→ DECERR); addresses straddling region boundaries; and (if applicable) AxREGION output correctness and security-check behavior. The highest-value tests are the boundary addresses (region edges — where decode off-by-ones hide) and the hole/DECERR cases (proving unmapped accesses error correctly rather than silently hitting a wrong slave). A complete address-map coverage matrix — every region, every boundary, every hole — is the core of decode verification, since the decoder's job is precisely to map addresses to ports correctly across the whole space.

8. Interview Questions

9. Summary

The decoder implements the interconnect's routing by mapping AxADDR to a subordinate port using the address map — the table assigning each subordinate a base+size region of the global address space. The decode process matches the address to a region (usually by high-bit comparison, enabled by power-of-two aligned regions) and routes the transaction there; an unmapped hole routes to a default slave returning DECERR, and the 4 KB rule lets a single start-address decode route a whole burst. The map's constraints are hard: no overlaps (ambiguous), holes are legal but error, and alignment enables cheap decode; the decoder may also drive AxREGION and incorporate AxPROT security checks.

Decode sits on the address path, so it's a latency-vs-frequency trade (combinational = low latency but critical-path; registered = +1 cycle but higher frequency), and its latency feeds the outstanding depth needed to hide it. Its bugs are routing problems — wrong-slave (map error/overlap), unexpected DECERR (unmapped/wrong address), missing DECERR (aliasing), timing (combinational on a big map), security leaks (missing AxPROT check) — all localizing to the map or decode logic. Verify the whole map: every region, every boundary, every hole, plus security. Next: the arbiter — how the per-subordinate arbitration that the decoder feeds resolves contention.

10. What Comes Next

You've got address decode; next, resolving the contention it creates:

12.4 — Arbiter & Arbitration (coming next) — the per-subordinate arbitration schemes (round-robin, fixed-priority, QoS-weighted) that resolve manager contention.
12.5 — Mux/Demux & ID-Based Routing (coming soon) — response routing by ID and ID-width remapping.

Previous: 12.2 — Crossbar Architecture. Related: 7.6 — The 4KB Boundary Rule for why one decode routes a burst, and 6.5 — AxPROT, AxQOS & AxREGION for region/security signals. For the broader protocol catalog, see the AMBA family overview doc.