AMBA AXI · Module 13
Bandwidth & Throughput
Defining and computing AXI bandwidth — peak (bus width × frequency) vs sustained throughput, the efficiency ratio, what limits it (overhead, outstanding depth, burst length, narrow transfers, contention), and the bandwidth formula.
Module 13 turns to performance, and it starts with the most fundamental metric: bandwidth. There are two numbers that matter — peak (theoretical) bandwidth, set by the bus width and clock, and sustained (effective) throughput, what you actually achieve, which is always lower. The ratio between them is efficiency, and understanding what drags sustained below peak — overhead, insufficient outstanding depth, short bursts, narrow transfers, contention — is the core of AXI performance work. This chapter defines the metrics, gives the bandwidth formula, and catalogs what limits throughput.
1. Peak vs Sustained
Two distinct numbers:
- Peak (theoretical) bandwidth = data bus width (bytes) × clock frequency. A 128-bit (16-byte) bus at 1 GHz has a peak of
16 × 10⁹ = 16 GB/s. It's the absolute ceiling — one full-width beat every cycle, forever. - Sustained (effective) throughput = the bandwidth actually achieved over real traffic — always less than peak, because real traffic has idle cycles (bubbles), addressing overhead, and underutilized beats.
The efficiency is sustained ÷ peak — what fraction of the ceiling you reach. A well-designed high-bandwidth path might hit 80–95% efficiency; a poorly-shaped one (short bursts, too few outstanding, narrow transfers) might be 20% or worse. Performance work is largely about raising efficiency — closing the gap between sustained and peak.
2. The Bandwidth Formula
Sustained throughput can be computed from the traffic:
Sustained throughput = (data beats transferred per second) × (bytes per beat) × utilization
equivalently, per transaction: bytes/transaction = (AxLEN+1) × 2^AxSIZE (from Chapter 7.1), so throughput = (transactions/sec) × (bytes/transaction). And utilization is the fraction of cycles the data channel actually transfers a beat (both VALID/READY high) — 1.0 is full rate, lower means bubbles.
The two levers in the formula: bytes per beat (the bus width, fixed by the data path) and utilization (how busy you keep the data channel). Since width is usually fixed, sustained throughput is mostly a utilization problem — keep the data channel transferring every cycle and you approach peak; let it idle (waiting on addresses, latency, or contention) and you fall short. So "improve bandwidth" almost always means "improve utilization."
bandwidth-calc — data-channel utilization (busy vs idle cycles)
8 cycles3. What Limits Sustained Throughput
The gap between peak and sustained comes from a handful of causes:
- Addressing/handshake overhead — cycles spent on address phases or stalls rather than data. Amortized by long bursts (one address per many beats), worsened by short bursts.
- Insufficient outstanding depth — if too few transactions are in flight to cover the latency, the data channel idles between them (latency-bound, Chapter 8.1). The dominant cause on high-latency paths.
- Short bursts — each burst pays an address-phase overhead; length-1 bursts can collapse throughput toward the address-channel rate. Longer bursts amortize it.
- Narrow transfers —
AxSIZEbelow the bus width uses only some byte lanes per beat, wasting bus bandwidth (Chapter 7.7). Full-width transfers use all lanes. - Backpressure / contention — a slow consumer or a contended shared subordinate inserts bubbles (Chapters 11.6, 12.4).
So the recipe for high sustained throughput is: long, full-width bursts with enough outstanding transactions to hide latency, to a non-contended path. Each limiter is an efficiency leak; closing them is the optimization work of the rest of Module 13.
4. Computing It in Practice
A worked approach: take a 128-bit bus (16 B) at 1 GHz → peak 16 GB/s. Suppose a DMA does 16-beat full-width INCR bursts (AxLEN=15, AxSIZE=4) = 16 × 16 = 256 bytes/transaction, with enough outstanding to keep the data channel ~95% utilized. Sustained ≈ 16 GB/s × 0.95 ≈ 15.2 GB/s (95% efficiency). Now suppose instead it does length-1 bursts with only 2 outstanding against a 20-cycle latency: it completes ~2 transactions per 20 cycles × 16 B = far below peak — maybe 10–20% efficiency, latency-bound.
The practical method: (1) compute peak (width × freq); (2) measure or estimate utilization (busy-cycle fraction of the data channel) — or derive the achievable depth from Little's law (throughput = outstanding ÷ latency) and compare to peak; (3) efficiency = sustained ÷ peak, and the shortfall points at the limiter (low depth → latency-bound; short bursts → overhead; narrow → lane waste; bubbles → contention). This decomposition — peak, then utilization, then the specific limiter — is how you diagnose and improve any AXI path's bandwidth.
5. Common Misconceptions
6. Debugging Insight
7. Verification Insight
8. Interview Questions
9. Summary
AXI bandwidth has two numbers: peak = bus width × frequency (the ceiling — a full-width beat every cycle) and sustained = what's actually achieved (always lower), with efficiency = sustained ÷ peak. The bandwidth formula — bytes/beat × beats-transferred-per-second (or per transaction, (AxLEN+1) × 2^AxSIZE × transactions/sec) — shows that since bytes/beat (width) is fixed, sustained throughput is mostly a utilization problem: keep the data channel transferring every cycle and you approach peak. The limiters that drag sustained below peak are insufficient outstanding depth (latency-bound — the dominant one, via Little's law), short bursts (unamortized address overhead), narrow transfers (wasted lanes), and backpressure/contention (bubbles).
The diagnosis flow is peak → utilization → limiter: compute the ceiling, measure the busy-cycle fraction (or derive achievable depth from throughput = outstanding ÷ latency), get efficiency, and the shortfall names the limiter. The high-throughput recipe is long, full-width bursts with enough outstanding depth to hide latency on a non-contended path. Critically, bandwidth bugs are correct-data-but-slow — invisible to functional verification — so they demand dedicated measurement (throughput/efficiency monitors, depth sweeps) under realistic latency, or they ship as performance failures. Next: latency analysis — decomposing where the cycles of a transaction actually go.
10. What Comes Next
You've got the bandwidth metrics; next, the other half of performance:
- 13.2 — Latency Analysis (coming next) — decomposing a transaction's latency into its contributors (address, decode, slave, response, interconnect).
- 13.3 — Outstanding Depth & Buffering (coming soon) — sizing outstanding depth and buffers to hide latency.
Previous: 12.7 — Clock & Reset in Interconnect. Related: 8.1 — Why Outstanding Transactions Exist for the Little's-law foundation, and 7.1 — Burst Length, Size & Beats for the bytes-per-transaction formula. For the broader protocol catalog, see the AMBA family overview doc.