AMBA AXI · Module 14

Asynchronous AXI Bridges

The asynchronous AXI bridge structure — five per-channel async FIFOs crossing a full AXI interface between clock domains, how flow control and the handshake are reconstructed on each side, and the latency/depth and bridge-type trade-offs.

Chapter 14.1 established why AXI needs an async FIFO per channel to cross clock domains safely; this chapter is the concrete bridge structure. An asynchronous AXI bridge crosses a full AXI interface between two clock domains using five per-channel async FIFOs (one for each of AW, W, B, AR, R), presenting a clean AXI port in each domain. We'll cover the bridge's structure and per-channel directions, how the VALID/READY handshake is reconstructed on each side from the FIFO full/empty flags, the latency and depth implications, and the bridge-type choices (full-async vs rational). This is exactly the interconnect's clock converter (Chapter 12.7), made concrete.

1. The Five-Channel Bridge

An async AXI bridge crosses the whole interface with one async FIFO per channel, each crossing in the direction that channel's traffic flows:

Forward channels — AW (write address), W (write data), AR (read address) — written in the manager-side domain, read in the subordinate-side domain.
Response channels — B (write response), R (read data) — written in the subordinate-side domain, read in the manager-side domain.

The bridge presents a complete AXI subordinate interface on the manager side (clocked by the manager's clock) and a complete AXI manager interface on the subordinate side (clocked by the subordinate's clock). Between them, the five FIFOs carry the traffic across the boundary. So from each side's perspective it's a normal AXI port — the clock-domain crossing is hidden inside the bridge.

Figure 1 — the five-channel async AXI bridge. Each AXI channel has its own async FIFO: forward channels (AW, W, AR) cross manager-domain → subordinate-domain; response channels (B, R) cross subordinate-domain → manager-domain. The bridge presents a full AXI subordinate port (manager clock) on one side and a full AXI manager port (subordinate clock) on the other; the CDC is hidden inside.

2. One Channel's Async FIFO

Each channel's crossing is the async FIFO from Chapter 14.1, made concrete for an AXI channel: it carries that channel's payload (e.g., for AW: AWADDR, AWLEN, AWSIZE, AWID, … packed into one FIFO word) across the boundary:

Write side (source domain): when the source presents a valid beat (channel VALID high) and the FIFO isn't full, the beat is written into the FIFO.
Read side (destination domain): when the FIFO isn't empty, a beat is available to be read and presented (channel VALID high) to the destination.
Dual-clock memory + Gray pointers: the payload rides through the memory (read only when present — no metastable sampling), and the write/read pointers cross domains Gray-coded through synchronizers for safe full/empty computation (14.1).

So one FIFO carries one channel's entire payload as a unit — all that channel's signals packed together — guaranteeing the payload stays coherent across the crossing (no VALID-before-data-stable, no bit skew). Packing the channel's signals into a single FIFO word is what keeps them associated, solving the multi-signal-coherence problem of 14.1.

Figure 2 — one channel's async FIFO. The channel's full payload (e.g., AWADDR/AWLEN/AWSIZE/AWID packed together) is written as one FIFO word in the source domain and read in the destination domain only when present. Dual-clock memory carries the data; Gray-coded pointers cross via synchronizers for safe full/empty. Packing the channel's signals into one word keeps them coherent across the crossing.

3. Reconstructing the Handshake and Flow Control

The bridge reconstructs the VALID/READY handshake on each side from the FIFO's flags, preserving AXI flow control across the boundary:

Write side: the FIFO's full flag drives the channel's READY — when the FIFO is full, the bridge deasserts READY to the source, backpressuring it (Chapter 11.6). The source holds its data until space frees. So a downstream domain that can't keep up naturally backpressures the upstream through the FIFO.
Read side: the FIFO's not-empty flag drives the channel's VALID — when the FIFO has a beat, the bridge asserts VALID to the destination; the destination's READY controls the read.

So each side sees a normal AXI handshake: the manager-side port backpressures (via READY) when the bridge's forward FIFOs fill, and the subordinate-side port sees VALID as forward data arrives. The handshake's coupling (data stable while VALID held until READY) is satisfied because the FIFO holds the data stable until read. This is how the bridge appears as a transparent AXI port to each domain while safely crossing the boundary — the FIFO full/empty flags are the reconstructed flow control.

Figure 3 — handshake reconstruction and flow control. On the write side, the FIFO full flag drives READY (full → deassert READY → backpressure the source). On the read side, the FIFO not-empty flag drives VALID (data present → assert VALID). Each side sees a normal AXI handshake; the FIFO flags reconstruct the VALID/READY flow control across the crossing, and the held data satisfies the stability rule.

4. Latency, Depth, and Bridge Types

Design considerations and variants:

Latency: each FIFO crossing adds a few cycles each way (write-to-read synchronization + FIFO traversal). This CDC latency adds to the transaction latency (Chapter 13.2), which raises the outstanding depth needed to hide it (Chapter 13.3) — so a master behind an async bridge needs more in-flight transactions to sustain throughput across the added latency.
FIFO depth: sized for two things at once — to absorb rate mismatch (a faster source filling while a slower destination drains, Chapter 11.6) and to hold enough outstanding transactions to cover the CDC latency (the bandwidth-latency product). Too shallow → backpressure/latency-bound; sized right → sustains throughput up to the slower domain's rate.
Bridge types: a fully asynchronous bridge handles any clock relationship (arbitrary, unrelated frequencies) using the Gray-pointer async FIFO — the general, safe case. A rational/synchronous bridge, where the clocks have a known integer ratio (or share an edge), can be simpler/cheaper (fewer synchronizer stages, deterministic latency) but only works for that constrained relationship. Use full-async unless the clocks are guaranteed related.

So the bridge is a latency-vs-area-vs-generality trade: full-async FIFOs (general, more latency/area) sized for the rate mismatch and CDC latency, with outstanding depth budgeted accordingly. Reset coordination across the two domains is also required (Chapter 14.3).

Figure 4 — design considerations and bridge types. CDC latency (FIFO + synchronizer) adds to transaction latency, raising the outstanding depth needed; FIFO depth is sized for both rate-mismatch absorption and outstanding coverage of the CDC latency. Bridge types: fully-asynchronous (any clock relationship, Gray-pointer FIFO — general) vs rational/synchronous (known integer ratio — simpler/cheaper but constrained). Use full-async unless clocks are guaranteed related.

5. Common Misconceptions

Myths to unlearn

"One FIFO crosses the whole AXI interface." No — five FIFOs, one per channel (AW/W/B/AR/R), each crossing in its traffic's direction. The channels are independent and cross independently.
"The bridge changes the protocol." It doesn't — each side sees a normal AXI port (subordinate port on the manager side, manager port on the subordinate side); the CDC is hidden inside, and AXI semantics are preserved.
"The handshake doesn't survive the crossing." It's reconstructed from the FIFO flags: full → READY deasserts (backpressure), not-empty → VALID asserts. Flow control crosses correctly via the FIFO.
"An async bridge has no throughput/latency cost." It adds CDC latency (raising the outstanding depth needed) and its FIFO depth must be sized for rate mismatch + outstanding — it's not free.
"Use a rational bridge always (it's simpler)." Only if the clocks have a guaranteed integer ratio. For arbitrary/unrelated clocks you need a fully-asynchronous bridge; a rational bridge would be unsafe.
"FIFO depth only matters for rate mismatch." It also must hold enough outstanding transactions to cover the CDC latency (the BLP) — both concerns size it.

6. Debugging Insight

🔍 Debugging insight — bridge structure, flow control, and depth issues

Async-bridge problems fall into structural-CDC, flow-control, and sizing categories:

Intermittent corruption across the bridge? A structural CDC flaw (Chapter 14.1) — a channel not crossing through a proper async FIFO, a non-Gray-coded pointer, or per-bit synchronizing. Run static CDC analysis; functional sim won't catch it.
A channel hangs / backpressures permanently? The handshake reconstruction is wrong — READY not driven from the FIFO full flag, or VALID not from not-empty. Check the flag-to-handshake mapping per channel.
Throughput below the slower domain's rate? FIFO too shallow — it can't hold enough outstanding to cover the CDC latency (the BLP grew with the crossing latency, Chapter 13.3) or absorb the rate mismatch. Deepen the FIFOs and/or raise outstanding depth.
Works at some clock ratios, fails at others? A rational bridge used where the clocks aren't actually a fixed integer ratio — switch to a fully-asynchronous bridge for arbitrary relationships.
Glitches/hangs around reset? Reset not coordinated across the two domains (Chapter 14.3) — the FIFO pointers/state initialized inconsistently. Coordinate resets across domains.

The triage: cross-domain corruption → structural CDC (static analysis); channel hang → handshake-reconstruction mapping; slow → FIFO depth / outstanding for CDC latency; ratio-dependent → rational-vs-async mismatch; reset glitch → reset coordination. CDC structural issues need static analysis; the rest are functional/sizing.

7. Verification Insight

✅ Verification insight — structural CDC plus functional data integrity across ratios

Verify the async bridge on two fronts. Structural CDC (the non-negotiable): static CDC analysis confirming every channel crosses through a proper async FIFO (data through memory, Gray-coded pointers, synchronized control — no per-bit data sync), since functional sim doesn't model metastability (Chapter 14.1). Functional integrity: an end-to-end scoreboard confirming every transaction crosses the bridge intact — each channel's payload arrives in the destination domain correctly and in order, every transaction gets its response back, none lost/duplicated — and that the handshake/flow control works (the bridge backpressures via READY when its FIFOs fill, asserts VALID when data is present).

Coverage must sweep a wide range of clock ratios — fast→slow, slow→fast, close-but-asynchronous, and (if a rational bridge) the exact supported ratios plus confirmation it's only used there. Include: FIFO full (backpressure) and empty (starvation) conditions; full outstanding load across the crossing (confirm depth sustains throughput, feeding the BLP); reset in each domain and coordinated reset (Chapter 14.3); and the per-channel independence (all five channels active concurrently). The highest-value checks are the static CDC structural proof (catches metastability-prone crossings sim misses) and the all-ratios functional integrity sweep (proves the bridge works for any asynchronous relationship, not just the testbench's convenient one). Together they confirm the bridge is both metastability-safe (structural) and protocol-correct (functional) across clock relationships — the complete async-bridge sign-off.

8. Interview Questions

9. Summary

An asynchronous AXI bridge crosses a full AXI interface between clock domains with five per-channel async FIFOs: forward channels (AW/W/AR) cross manager→subordinate, response channels (B/R) cross subordinate→manager, and the bridge presents a normal AXI port (subordinate-side on the manager domain, manager-side on the subordinate domain) hiding the CDC inside. Each FIFO packs its channel's payload into one word (keeping the signals coherent), carries it through dual-clock memory (read only when present), and crosses Gray-coded pointers via synchronizers (14.1). The VALID/READY handshake is reconstructed from the FIFO flags — full → READY deasserts (backpressure), not-empty → VALID asserts — so each side sees normal AXI flow control.

The trade-offs: the bridge adds CDC latency (raising the outstanding depth needed to hide it, Module 13), and its FIFO depth is sized for both rate-mismatch absorption and outstanding coverage of that latency. Bridge types: fully-asynchronous (any clock relationship — the safe general case) vs rational/synchronous (known integer ratio — simpler/cheaper but constrained). It must be co-verified structurally (static CDC — metastability safety) and functionally (AXI protocol + data integrity across clock ratios) and for performance (throughput across the crossing) — the convergence of CDC, protocol, and performance, which is why it's usually verified IP. Next: reset sequencing — ARESETn behavior and the synchronous-deassert discipline.

10. What Comes Next

You've got the async bridge; next, coordinating reset across it:

14.3 — Reset Sequencing (coming next) — ARESETn behavior, synchronous-deassert reset discipline, and coordinating reset across clock domains.

Previous: 14.1 — AXI Across Clock Domains. Related: 12.7 — Clock & Reset in Interconnect for where this sits in the fabric, and 13.3 — Outstanding Depth & Buffering for the depth the CDC latency demands. For the broader protocol catalog, see the AMBA family overview doc.