VHDL · Topic
VHDL Testbenches — Stimulus, Checking & Self-Checking Design
Writing VHDL testbenches — entity-less top levels, stimulus processes, clock generation, assertions and self-checking structure.
A VHDL testbench is an entity with no ports, which is the language stating plainly that it connects to nothing outside itself. Everything else follows from that: the testbench instantiates the design, generates its own clock and reset, drives stimulus from processes, and decides for itself whether what came back was right. The step that separates a demonstration from a test is the last one — a testbench that prints values requires a human to read them, and a self-checking testbench does not.