VHDL · Topic
VHDL Signals vs Variables — Assignment & Delta Cycles
Signal assignment semantics, variables, delta cycles and the scheduling model that decides when a value is actually seen.
A signal assignment does not take effect immediately — it schedules a value that becomes visible in the next delta cycle, so a signal read later in the same process still returns the old value. A variable assigns immediately. That single difference explains most early VHDL confusion, and it is not a quirk: signals model wires, which cannot change instantaneously in response to themselves, and variables model local computation, which can.