VHDL · Topic
VHDL Processes — Sensitivity Lists & Sequential Statements
Processes, sensitivity lists, if/case statements, loops and wait — sequential description inside a concurrent language.
A process is the one place in VHDL where statements execute in order, and its sensitivity list is what decides when that execution happens at all. An incomplete sensitivity list is the classic combinational bug: the process does not re-evaluate when an input it reads changes, so simulation shows a stale value while synthesis — which ignores the list — builds the circuit you meant. The two disagree, and only simulation is wrong.