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VHDL Data Types — std_logic, Vectors, Arrays & Records

std_logic and std_logic_vector, integers, arrays, records and subtypes — VHDL's type system and why it rejects what other HDLs accept.

VHDL is strongly typed to a degree that surprises engineers arriving from Verilog, and the strictness is the feature. An assignment between two types of the same width is an error unless a conversion is written, which means a whole class of width and interpretation bugs becomes a compile failure rather than a silent mismatch. The cost is conversion noise; the benefit is that the compiler catches what simulation would otherwise have to.

Lessons in this topic(13)

Start hereThe VHDL Type System and Strong TypingVHDL Type System and Strong Typing
  1. 2The Nine Values of std_logic
  2. 3std_logic vs bit and boolean
  3. 4std_logic_vector and Buses
  4. 5Resolved vs Unresolved Types
  5. 6Integer Types and Ranges
  6. 7Enumeration Types
  7. 8numeric_std: signed and unsigned
  8. 9Type Conversions and Casting
  9. 10Array Types
  10. 11Record Types
  11. 12Subtypes and Range Constraints
  12. 13Physical Types and time