VHDL · Topic
VHDL Concurrent Statements — Signal Assignment & Generate
Concurrent signal assignment, conditional and selected assignment, blocks and generate statements — describing hardware that all runs at once.
Everything written in a VHDL architecture body outside a process executes concurrently, which is a truer description of hardware than any sequential language offers. The mental adjustment is that order of writing carries no meaning: two concurrent assignments in either order describe the same circuit. Generate statements extend the same idea to structure, replicating hardware at elaboration time in a way no procedural loop can.