UVM RAL · Topic
UVM RAL Register Model — Fields, Registers & Blocks
Building a UVM register abstraction layer — fields, registers, register blocks, address maps and how the model mirrors the DUT.
A register model is a second, independent description of the design's register map, and its value comes entirely from that independence. It lets a test say 'write this field' rather than 'write these bits at this address', and it lets a scoreboard know what the DUT should now contain without re-deriving it. The risk is the same independence in reverse: a model generated from a stale specification confidently checks the wrong thing.