UVM RAL · Topic
UVM RAL Adapters — reg2bus and bus2reg
Register adapters — translating generic register operations into bus transactions and back, and the conversions that silently lose information.
An adapter is the seam between a protocol-independent register model and a protocol-specific agent, which means it is where information is most easily lost. `reg2bus` must carry byte enables, address alignment and access kind into the bus item; `bus2reg` must recover them faithfully or prediction breaks. An adapter that drops a byte enable produces a model that believes a partial write was a full one — and the mismatch surfaces much later, as a register that reads back wrong for no visible reason.