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Learnings · UVM · Labs

UVM labs.

Build a real UVM environment one piece at a time — component tree, factory, TLM, monitor, scoreboard, agent — finishing with a working APB capstone.

0of 7 labs live7 phases · grouped by difficulty
Lab Philosophy

Small, working pieces of silicon-grade code.

UVM only clicks when you build one. These labs walk a single APB project from a one-component hierarchy to a complete agent/env with regression — every step solves one real verification problem, never just methodology trivia.

Lab Roadmap

7-phase progression.

  1. 01Component Tree1
  2. 02Transactions1
  3. 03Stimulus1
  4. 04Observability1
  5. 05Checking1
  6. 06Architecture1
  7. 07Capstone1

All Labs

Grouped by difficulty

Foundation

2 labs
  1. Lab 01

    UVM Component Hierarchy Lab

    Build a three-level component tree (env → agent → driver) and walk the hierarchy with `print_topology()`.

    Skills practiced
    • uvm_component
    • build_phase
    • print_topology
    Deliverable
    A minimal env that prints its topology + a one-line explanation of each phase's role.
    FoundationPlannedComponent Tree
  2. Lab 02

    Sequence Item & Factory Lab

    Define a transaction with field macros, register it with the factory, and override it from a test.

    Skills practiced
    • uvm_sequence_item
    • Field macros
    • Type overrides
    Deliverable
    A base transaction + an override transaction selected per-test with `factory.set_type_override_by_type()`.
    FoundationPlannedTransactions

Intermediate

3 labs
  1. Lab 03

    Sequencer–Driver Handshake Lab

    Wire a sequencer and driver with `get_next_item()` / `item_done()` and a TLM port hand-off.

    Skills practiced
    • uvm_sequencer
    • uvm_driver
    • TLM blocking
    Deliverable
    A working seq → drv hand-off pumping 100 transactions to a stub DUT.
    IntermediatePlannedStimulus
  2. Lab 04

    Monitor & Analysis Port Lab

    Sample DUT signals into a monitor and broadcast transactions via an analysis port to two subscribers.

    Skills practiced
    • uvm_monitor
    • uvm_analysis_port
    • uvm_subscriber
    Deliverable
    A monitor feeding both a coverage collector and a scoreboard from one analysis port.
    IntermediatePlannedObservability
  3. Lab 05

    Scoreboard Lab

    Compare expected vs actual transactions using a uvm_in_order_comparator and a custom mismatch report.

    Skills practiced
    • Scoreboards
    • Reference models
    • Comparator policy
    Deliverable
    A scoreboard that catches two seeded RTL bugs and emits a readable mismatch trace.
    IntermediatePlannedChecking

Advanced

2 labs
  1. Lab 06

    Agent / Environment Integration Lab

    Compose a passive + active agent inside one environment and switch modes with `is_active`.

    Skills practiced
    • Agent composition
    • uvm_active_passive_enum
    • config_db
    Deliverable
    An env that swaps between active driving and passive monitoring from a test-level config.
    AdvancedPlannedArchitecture
  2. Lab 07

    APB UVM Mini-Project Lab

    Capstone — build a complete UVM environment for an APB slave: agent, scoreboard, register model, and three smoke tests.

    Skills practiced
    • Full UVM stack
    • uvm_reg
    • Smoke regression
    Deliverable
    A working APB UVM env with regression of three tests passing against a reference RTL.
    AdvancedPlannedCapstone