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SystemVerilog · Topic

SystemVerilog OOP — Classes, Inheritance & Polymorphism

Classes, handles, constructors, inheritance, virtual methods and parameterised classes — the object model every UVM testbench is built on.

SystemVerilog's class system exists because a testbench is not a circuit. Stimulus, transactions and checkers are data that come and go during a run, and the language needed a way to describe things with a lifetime rather than a fixed set of wires. The consequence engineers meet first is handles: a class variable holds a reference, not an object, so assignment copies the handle and two variables end up naming the same object. Almost every early class-based bug is that distinction, and the copy/clone machinery exists to resolve it.

Lessons in this topic(16)

Start hereIntroduction to OOP in SystemVerilogIntroduction to OOP in SystemVerilog
  1. 2Classes & Objects — Basics
  2. 3Properties & Methods
  3. 4Constructors & new()
  4. 5Encapsulation — public, protected, local
  5. 6The this Keyword
  6. 7Static Properties & Methods
  7. 8Inheritance & extends
  8. 9The super Keyword
  9. 10Polymorphism & Virtual Methods
  10. 11Abstract Classes & Pure Virtual Methods
  11. 12Parameterised Classes
  12. 13Nested Classes
  13. 14Handles — Shallow Copy, Deep Copy, Comparison
  14. 15typedef class — Forward Declarations
  15. 16Class Scope Resolution (::)