SystemVerilog · Topic
SystemVerilog Interfaces, Modports & Clocking Blocks
Interfaces, modports, clocking blocks and virtual interfaces — bundling a protocol once and connecting testbench to DUT without race conditions.
An interface exists to stop a protocol's signal list being retyped in every module that touches it, but its more important job is timing. A clocking block gives testbench code a defined sampling and driving skew relative to the clock, which is what removes the race between a driver writing a signal and a monitor reading it in the same timestep. A testbench that samples DUT outputs without a clocking block works until it doesn't, and the failure is schedule-order dependent — the hardest kind to reproduce.