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SystemVerilog · Topic

SystemVerilog Data Types — 2-State, 4-State & Nets

logic, bit, int, integer, nets and user-defined types — what each can hold, when X matters, and which choice changes hardware.

The type you declare decides three things at once: what values the object can hold, whether the tool will let you drive it from more than one place, and whether an uninitialised read is visible. Choosing `int` over `integer` in a counter is not style — a 4-state counter starts at X and stays X, and `%0d` prints that as zero, so the bug looks like a counter that never counted. Most type decisions in this cluster are of that shape: the wrong choice is legal, compiles clean, and hides its own symptom.

Lessons in this topic(9)

Start here4-State vs 2-State TypesSystemVerilog 4-State vs 2-State Types
  1. 2Integer Types
  2. 3Real & Shortreal Types
  3. 4String Type & Methods
  4. 5User-Defined Types with typedef
  5. 6Enumeration Types
  6. 7Structures — Packed & Unpacked
  7. 8Unions & Tagged Unions
  8. 9Type Casting & Conversion