Packages

Module 16 · 4 Pages

Packages

The modular-design foundation that turns a SystemVerilog codebase into a maintainable, reusable system. Module 16 covers the four primitives that take a package from a one-line skeleton to the canonical pattern every production VIP (and every UVM environment) is built on — declaration, import semantics, package-level parameters and types, and the compilation-order discipline that keeps a multi-package build sane.

• Package Declaration & Usage
• import — Explicit & Wildcard
• Package-Level Parameters & Types
• Package Dependencies & Compilation Order

Architectural arc: §1 (declaration & usage) introduces the named scope and the :: operator that gives any consumer unambiguous access. §2 (import) covers the shorthand that drops the pkg_name:: prefix, the explicit-vs-wildcard distinction, and the name-resolution priority rules. §3 (package-level parameters & types) shows the canonical pattern for protocol constants and shared transaction types. §4 (compilation order) closes the module with the dependency discipline that keeps multi-package elaboration deterministic.

Companion: the per-symbol scope-resolution treatment at /learnings/systemverilog/scope-resolution (Module 9.16) covers :: in the class and super contexts; this module covers the package context end-to-end.