GLS · Chapter 2 · Netlists & Standard-Cell Libraries

specify Blocks & Timing Arcs

The specify block inside a cell's Verilog model is where gate-level timing attaches, and understanding it clarifies where a simulation's delays come from. A specify block declares the cell's timing arcs, its pin-to-pin propagation paths written from an input pin to an output pin with a delay, and for sequential cells its timing checks. The crucial point is that the delay values in a specify block are placeholders, typically zero or a nominal number, meant to be overridden per instance by an SDF file back-annotated later. So the specify block defines the structure of a cell's timing, which pins connect to which outputs and where a delay belongs, but not the real numbers, which come from the SDF. This lesson dissects a representative specify block and shows why having one does not mean a run has real timing.

Foundation12 min readGLSspecifyTiming ArcsSDFDelays

Chapter 2 · Section 2.4 · Netlists & Standard-Cell Libraries

Project thread — the counter's flop and gates each carry specify arcs (CK→Q, A→Y). Those arcs are empty vessels until 2.6/Chapter 4 fills them with SDF numbers — which is why a bare counter GLS updates 'instantly.'

1. Why Should I Learn This?

'Where does a gate-level simulation's timing come from?' is one of the most confused questions in verification, and the specify block is the answer's missing half. Every cell model has a specify block, yet a bare GLS run is zero-delay — because the block's delay values are placeholders until an SDF back-annotates them (Chapter 4). Knowing that specify defines the arc structure while SDF supplies the values is what lets you reason precisely about why a run is (or is not) timed, and where real delays enter.

This lesson opens the timing half of the cell model 2.3 gave you (the function half), and it bridges directly into 2.5 (the sequential timing checks that live inside specify) and Chapter 4 (SDF, which fills these arcs).

2. Real Silicon Story — the specify block that had arcs but no delays

An engineer inspects a cell's Verilog model, sees a full specify block — arcs for every pin-to-pin path, $setup and $hold checks — and concludes the model 'carries its timing,' so a GLS run using it must be timed. They report timing behaviour as exercised. A later SDF-annotated run behaves differently, exposing a timing-sensitive issue the earlier run missed.

The specify block was present but its delay values were the default placeholders — 0 (or a nominal figure that the flow treats as a stand-in). A specify block declares the arcs — the structure of the cell's timing, which pins connect to which outputs — but the real, per-instance delay numbers come only from an SDF back-annotated onto those arcs (Chapter 4), and no SDF had been applied. So the arcs were empty vessels: the timing shape was there, but every arc contributed zero delay, making the run effectively zero-delay. Once the SDF (characterised from the .lib, for the right corner) was back-annotated, the arcs carried real delays and the timing behaviour appeared. The post-mortem lesson: a cell model's specify block declares the timing arcs (the structure of its timing) with placeholder delay values; the real delays are supplied per instance by an SDF back-annotated later (Chapter 4) — so a model having a specify block does not mean a run is timed; specify is the shape, SDF is the values.

3. Concept — the timing arc, and the placeholder-vs-SDF split

The specify block lives inside a cell's Verilog model and declares its timing:

Timing arc — a pin-to-pin propagation path: (A => Y) = delay; means 'a transition on input A propagates to output Y after delay.' The arc is the atom of gate-level timing. (=> is a parallel/scalar connection; *> a full connection — both name arcs.)
Conditional arcs — if (S) (A => Y) = d1; lets delay depend on state (state-dependent paths).
Timing checks — for sequential cells, specify also holds $setup, $hold, $width, etc. (2.5).
The delay values are placeholders. They are 0 or nominal by default — not the real numbers. They are meant to be overridden.
SDF supplies the real values, per instance. An SDF (characterised from the .lib, 2.2, for a corner) is back-annotated (Chapter 4), replacing the placeholders with real per-instance delays. ASIC context: SDF matches the corner STA signed off.
So: specify = structure (which arcs exist); SDF = values (the real delays). Without SDF, the arcs exist but contribute placeholder (≈zero) delay — the run is effectively zero-delay (0.4).

Here is how a transition flows through an arc, and where the value comes from:

Figure 1 — a timing arc, and where its delay comes from (representative). An INPUT transition on pin A propagates through the cell model's specify ARC (A => Y) to produce an OUTPUT transition on Y, delayed by the arc's value. But the specify block only defines the arc's STRUCTURE — its delay value is a PLACEHOLDER (0 / nominal). The REAL per-instance delay is supplied by an SDF, back-annotated onto the arc (Chapter 4). Without SDF the arc contributes placeholder (approx zero) delay -> effectively zero-delay. specify = shape; SDF = values.

4. Mental Model — the specify block is the wiring for timing; the SDF is the current

Mental Model — specify blocks are empty pipes (the arcs); the SDF is what flows through them — pipes with no flow means an effectively zero-delay run

Think of a cell's specify block as a set of labelled pipes connecting input pins to output pins — the timing arcs. The pipes define where delay can flow (which pin affects which output), but the pipes ship empty: their delay values are placeholders. The SDF is the water — the real per-instance delays — poured into those pipes by back-annotation. Pipes with no water is a run with no real timing.

Picture the cell's timing as plumbing. The specify block installs the pipes — each arc (A => Y) is a labelled pipe saying 'a change on A reaches Y through here.' Installing the pipes is essential: without an arc, there is no path for delay between those pins at all. But the pipes arrive empty — the delay number written in the specify block is a placeholder (0 or nominal), a stand-in, not the real transit time. The water — the actual per-instance delays — comes from the SDF, poured into the pipes by back-annotation (Chapter 4). So a cell model having a specify block tells you the pipes are installed (the timing structure exists), but it tells you nothing about whether water is flowing (whether real delays are present). A bare GLS run — pipes installed, no water — is effectively zero-delay, even though every model is full of specify arcs. This dissolves the confusion 'the model has a specify block, so my sim is timed': the block is the shape of the timing, not its values. It also cleanly frames the division of labour across the chapter: specify (this lesson) = the arcs, the structure; SDF (Chapter 4) = the numbers, characterised from the .lib (2.2). And it clarifies scope: even with the pipes full (SDF annotated), GLS only pushes water through the paths your stimulus exercises — it does not, unlike STA, statically check every pipe (0.3).

Two anchors:

specify = arcs (structure); SDF = delays (values). The block defines which pins arc to which outputs; the SDF supplies the real per-instance numbers (Ch4).
A specify block present ≠ a timed run. Its delay values are placeholders — without SDF the arcs contribute ≈zero delay, so the run is effectively zero-delay (0.4).

5. Working Example — a representative specify block (arcs with placeholder delays)

Here is a representative specify block for a simple combinational cell — the arc structure, with placeholder delays.

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Snippet

// specify block inside a 2-input AND cell model — REPRESENTATIVE (shape only)
module AND2X1 (Y, A, B);
  output Y; input A, B;
  and (Y, A, B);                 // function (2.3)
  specify
    // timing ARCS — pin-to-pin paths. Delay values are PLACEHOLDERS (0), overridden by SDF (Ch4).
    (A => Y) = 0;                // arc: A -> Y
    (B => Y) = 0;                // arc: B -> Y
  endspecify
endmodule

The arcs (A => Y) and (B => Y) are present — the timing structure is defined — but the values are 0, placeholders. An SDF later replaces them per instance:

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Snippet

# SDF (Chapter 4) — REPRESENTATIVE — supplies the REAL delay for a SPECIFIC instance's arc:
(INSTANCE u_and0)
  (DELAY (ABSOLUTE
    (IOPATH A Y (0.084))     # overrides the (A => Y) placeholder for THIS instance
    (IOPATH B Y (0.091)))))
# Without this SDF back-annotation, (A => Y) stays 0 -> the AND output updates with ZERO delay.

Same model, two states: without SDF the arc delay is 0 (zero-delay); with SDF back-annotation the arc carries 0.084 for this instance. specify gave the arc; SDF gave the value. A sequential cell's specify also holds timing checks — the subject of 2.5:

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Snippet

// A sequential cell's specify ALSO carries timing checks (previewed here; detailed in 2.5)
specify
  (CK => Q) = 0;                       // clk-to-Q arc (placeholder -> SDF)
  $setup (D, posedge CK, 0);           // setup check (constraint value also from SDF/lib)
  $hold  (posedge CK, D, 0);           // hold check
endspecify

6. Debugging Session — "the model has a specify block, so my run is timed"

A gate-level run is assumed to be timed because every cell model has a specify block — but specify delay values are placeholders (0/nominal), so without an annotated SDF the arcs contribute zero delay and the run is effectively zero-delay

specify = ARCS (STRUCTURE); SDF = DELAYS (VALUES)

Symptom

An engineer sees that every cell model contains a full specify block — arcs, $setup/$hold checks — and concludes the GLS run 'carries its timing' and is therefore timed. A later SDF-annotated run behaves differently and reveals a timing-sensitive issue the earlier run did not show.

Root Cause

Confusing the structure of timing with its values. A specify block declares the cell's timing arcs — (A => Y) = delay; — which define which input pins propagate to which outputs: the shape of the cell's timing. But the delay values in a specify block are placeholders, 0 or nominal by default; they are not the real numbers and are meant to be overridden. The real, per-instance delays come only from an SDF — characterised from the .lib (2.2) for a corner — back-annotated onto those arcs (Chapter 4). No SDF had been applied here, so every arc still held its placeholder (0) delay: the timing structure was present, but every arc contributed zero delay, making the whole run effectively zero-delay (0.4). The presence of specify blocks — even full ones with timing checks — says nothing about whether real delays are in effect; that depends entirely on whether an SDF was annotated. It is not a model bug or a simulation bug; it is a misreading of specify as values when it is structure.

Fix

For a timing run, back-annotate an SDF (for the correct corner, matching STA signoff) so the specify arcs carry real per-instance delays (Chapter 4) — only then is the run genuinely timed. For a functional run (equivalence, X/reset), the placeholder zero-delay is fine — just do not call it timed. The lesson: a cell model's specify block declares the timing arcs — the structure of its timing — with placeholder delay values; the real delays come per instance from an SDF back-annotated later (Chapter 4), so specify present does not mean a run is timed: specify = shape, SDF = values. Two scope caveats: a representative specify block shows the arc structure, not the exact vendor model (use the real models for signoff); and even a fully SDF-annotated GLS is not an exhaustive timing check — it exercises only stimulated paths, dynamically, whereas STA checks all paths statically (0.3), so GLS does not prove all timing.

7. Common Mistakes

Reading a specify block as real timing. Its delay values are placeholders (0/nominal); the real numbers come from an annotated SDF (Ch4).
Assuming a specify block present means a timed run. Without SDF, every arc contributes ≈zero delay — the run is effectively zero-delay (0.4).
Confusing arc structure with delay values. specify defines which arcs exist; SDF supplies what each is worth, per instance.
Ignoring corners. SDF (and the placeholder-overriding values) must match the process/voltage/temperature corner STA signed off (ASIC context).
Treating an SDF-annotated GLS as a full timing proof. It exercises only stimulated paths — STA checks all paths statically (0.3).

8. Industry Best Practices

Read specify as the timing structure, SDF as the values. Arcs define paths; SDF (Ch4) supplies the real per-instance delays.
Back-annotate an SDF for timing GLS. Only then do the specify arcs carry real delays — a bare model is placeholder (≈zero) delay.
Match the corner across .lib, SDF, and STA. Use the corner STA signed off, for an ASIC-consistent timing picture.
Label runs by timing mode. specify-only (placeholder, zero-delay) vs SDF-annotated (real timing) — do not conflate (0.4).
Keep GLS and STA roles distinct. SDF-annotated GLS is dynamic/stimulus; STA is static/exhaustive — GLS does not prove all paths (0.3).

Senior Engineer Thinking

Beginner: "Every cell model has a specify block with arcs and checks — so my gate sim is timed."
Senior: "The specify block gives me the arcs — the structure. The delay values are placeholders until I annotate an SDF. Did I annotate one, for the right corner? If not, those arcs are 0 and this is a zero-delay run."

The senior reads specify as timing structure and knows real delays arrive only via SDF back-annotation.

Silicon Impact

Mistaking specify structure for real timing has the familiar cost: believe a placeholder-delay run is 'timed,' skip the SDF-annotated run, and let timing-dependent functional bugs escape to silicon (the 0.3 post-layout escape) — surfacing as corner-sensitive, intermittent failures. The specify block is genuinely important — it is the scaffolding every real delay hangs on; without the arc, the SDF has nowhere to put a number. But scaffolding is not the building: the values come from an SDF characterised from the .lib (2.2) for the signoff corner, back-annotated in Chapter 4. And even then, GLS pushes timing only through stimulated paths — STA remains the exhaustive static check (0.3). Keeping 'structure vs values' and 'dynamic vs static' straight is what routes timing verification correctly and keeps timing bugs off the tape-out.

Engineering Checklist

Read the specify block as the timing structure (arcs), not as real delay values.
For a timing run, back-annotated an SDF so arcs carry real per-instance delays (Ch4).
Matched the corner across .lib, SDF, and STA (ASIC signoff context).
Labelled the run by mode (specify-only zero-delay vs SDF-annotated timed).
Did not treat an SDF-annotated GLS as an exhaustive timing proof (STA does that, 0.3).

Try Yourself

Write the representative AND2X1 model above with (A => Y) = 0; and drive a transition on A.
Observe: Y updates with zero delay — the arc exists but its placeholder value is 0.
Change: back-annotate an SDF (Chapter 4) giving (IOPATH A Y (0.084)) for that instance and re-run.
Expect: now Y changes 0.084 after A — the same arc, now carrying a real value. Prove it: specify gave the arc, SDF gave the number.

Any Verilog simulator supports specify blocks and SDF annotation; no paid tool is required. Real cell specify blocks and SDF are vendor/PDK artifacts, but the arc-plus-SDF mechanics are identical to the representative snippets.

Interview Perspective

Weak: "The specify block holds the cell's real delays."
Good: "The specify block declares the cell's timing arcs — pin-to-pin paths; the delay values are placeholders overridden by an SDF back-annotated later."
Senior: "specify is the structure of a cell's timing — which arcs exist — with placeholder values. SDF supplies the real per-instance numbers by back-annotation (Ch4). So a specify block present doesn't mean a run is timed; without SDF the arcs are ≈zero. And even SDF-annotated GLS is dynamic and stimulus-limited — STA is the exhaustive static check."

9. Interview / Review Questions

10. Key Takeaways

A cell model's specify block declares its timing arcs — pin-to-pin paths like (A => Y) = delay; — and (for sequential cells) its timing checks (2.5): the structure of the cell's timing.
The delay values in a specify block are placeholders (0/nominal), meant to be overridden; the real per-instance delays come only from an SDF back-annotated later (Chapter 4).
So specify = structure (which arcs exist); SDF = values (the real delays) — a cell model having a specify block does not mean a run is timed; without SDF the arcs are ≈zero (effectively zero-delay, 0.4).
Match the corner across .lib, SDF, and STA (ASIC context), and label runs by mode (specify-only vs SDF-annotated).
An SDF-annotated GLS is dynamic/stimulus-limited — it does not prove all timing paths; STA is the static/exhaustive check (0.3). Next: 2.5 — the sequential timing checks that live in specify.

Quick Revision

specify = the timing structure; SDF = the values. A specify block declares timing arcs ((A => Y) = delay) and (for sequential cells) timing checks — but the delay values are placeholders (0/nominal). Real per-instance delays come only from an SDF back-annotated later (Ch4). A specify block present ≠ a timed run — without SDF the arcs are ≈zero. SDF-annotated GLS is dynamic/stimulus-limited; STA is the exhaustive static check. Next: 2.5 — sequential cell models: notifiers & timing checks.