Reset Behaviour at the Gate Level

Chapter 7 · Section 7.1 · Reset & Initialization Debug

Project thread — the FSM's X (6.6) was fixed by connecting reset; the counter (Ch2–4) is reset every run. This chapter makes reset rigorous; 7.5 debugs a stuck reset on the counter.

1. Why Should I Learn This?

Reset is the only thing that gets a netlist out of X, and its two styles behave differently.

• Async reset acts immediately (reset pin); sync reset acts at the clock edge (D logic).
• Mixing them up mis-predicts when a flop leaves X.
• Polarity (RN active-low) decides which level asserts.

This grounds the whole reset chapter (7.2 startup, 7.3 release, 7.4 sequencing, 7.5 the counter).

2. Real Silicon Story — the reset that "didn't work" (it was synchronous)

An engineer asserted reset and expected the flops to clear immediately. In the waveform they stayed X for a cycle — "reset is broken."

The flops used a synchronous reset: synthesis had folded reset into the D path, so it only took effect on the next clock edge. With the clock stalled at that moment, reset simply hadn't been sampled yet. It was working exactly as a sync reset should — the expectation (immediate, async) was wrong.

Lesson: async and sync resets behave differently — async is immediate, sync waits for a clock edge. Know which your flops use before judging reset "broken."

3. Concept — async vs sync reset in the netlist

Asynchronous reset:

• Acts immediately, independent of the clock.
• Drives the flop's dedicated reset pin (RN).
• The flop's UDP reset row forces the output whenever reset is asserted (2.3) — no clock needed.
• Cell example: DFFRX1 (D flop with async RN).

Synchronous reset:

• Acts only at a clock edge.
• Synthesis folds it into the D logic (a mux: D = rst ? 0 : next).
• Takes effect on the next edge, like any data.
• Cell: a plain DFFX1 with reset in the surrounding logic.

Polarity:

• Standard cells often use active-low reset (RN): rst_n = 0 = asserted, rst_n = 1 = released.
• Get polarity wrong and "reset" holds the wrong level.

Framing:

• Reset brings flops out of X (2.6); the style sets when.
• Both styles are valid — different area/timing/noise trade-offs.
• The tricky part is async release timing (recovery/removal) — 7.3.

4. Mental Model — async reset is a wall switch; sync reset is a scheduled task

Two ways to turn a light off.

• Async reset = a wall switch: flip it and the light goes off now, no matter what (immediate, clock-independent).
• Sync reset = a scheduled task: the light goes off at the next scheduled tick (clock edge) — reliable, but not instant.
• Polarity is which switch position means "off" — active-low means down (0) is asserted.

If you expect the wall switch but wired a scheduled task, "nothing happened yet" isn't broken — it's just waiting for the tick.

5. Working Example — sync vs async reset (tri-HDL) and the netlist

The two reset styles in RTL, three languages:

// SystemVerilog — ASYNC reset (in sensitivity list) vs SYNC reset (clock only)
always_ff @(posedge clk or negedge rst_n)   // ASYNC: reacts to rst_n immediately
  if (!rst_n) q <= 1'b0; else q <= d;
 
always_ff @(posedge clk)                     // SYNC: reset sampled only at the edge
  if (!rst_n) q <= 1'b0; else q <= d;

// Verilog — async (edge-sensitive to reset) vs sync
always @(posedge clk or negedge rst_n) if (!rst_n) q <= 1'b0; else q <= d;  // ASYNC
always @(posedge clk)                   if (!rst_n) q <= 1'b0; else q <= d;  // SYNC

-- VHDL — async (reset in process sensitivity) vs sync (clock only)
process (clk, rst_n) begin
  if rst_n = '0' then q <= '0';            -- ASYNC: immediate
  elsif rising_edge(clk) then q <= d; end if;
end process;

The netlist mapping:

// Netlist mapping — REPRESENTATIVE
DFFRX1 u_async (.D(d), .CK(clk), .RN(rst_n), .Q(q));         // ASYNC: reset via RN pin (immediate)
// SYNC: reset folded into D logic, plain flop:
assign d_sync = rst_n ? next : 1'b0;                          // reset mux on D
DFFX1  u_sync  (.D(d_sync), .CK(clk), .Q(q));                 // SYNC: takes effect at next edge

Practical context (representative, tool-neutral):

# Read reset from the waveform (tool-neutral):
#   flop clears the instant rst_n falls, no clock needed .... ASYNC (RN pin)
#   flop clears only at the next posedge clk .............. SYNC (reset in D logic)
#   rst_n = 0 asserts (active-low RN) ..................... check polarity!
#   flop stays X after reset ............................. reset not reaching it (7.4) or wrong style

Async (immediate) vs sync (at edge) reset, as a real waveform:

6. Debugging Session — "reset didn't work" (it was synchronous)

7. Common Mistakes

• Expecting immediate clearing from a sync reset. Sync reset waits for a clock edge.
• Expecting a sync flop to need an edge when it's async. Async clears immediately.
• Getting polarity wrong. RN is active-low — rst_n = 0 asserts.
• Not advancing the clock during a sync reset. It's never sampled without an edge.
• Assuming reset style from RTL alone. Read the netlist (RN pin vs D-mux).

8. Industry Best Practices

• Identify each flop's reset style from the netlist (RN pin vs D-logic).
• Match stimulus to style — clock during a sync reset; check async is immediate.
• Verify polarity explicitly (active-low RN).
• Use async reset where a known pre-clock state is required.
• Keep release timing in mind (async recovery/removal, 7.3).

Senior Engineer Thinking

• Beginner: "I asserted reset and the flop is still X — reset is broken."
• Senior: "Is it a sync reset? Then it clears at the next edge — is the clock running? Or is polarity backwards? Let me read the flop: RN pin means async, D-mux means sync."

The senior identifies the reset style and polarity from the netlist before judging reset broken.

Silicon Impact

Reset style is a correctness property, not a detail. A block that needs a known state before the first clock but was built with a synchronous reset can power up in an undefined state on real silicon (no edge yet) — a startup hazard. Conversely, an unnecessary async reset costs area/timing and adds release-timing risk (7.3). Reading reset behaviour correctly at the gate level — async vs sync, right polarity, reaching every flop — is the foundation of a clean bring-up. Misjudging it in simulation (calling correct sync behaviour "broken") wastes debug time; misjudging it in design can strand a block in X at power-up.

Engineering Checklist

• Identified each flop's reset style from the netlist (RN pin vs D-mux).
• Matched stimulus to the style (clock during sync reset).
• Verified polarity (active-low RN).
• Used async reset where a pre-clock known state is required.
• Noted release timing as a separate concern (7.3).

Try Yourself

1. Instantiate a DFFRX1 (async, RN) and a sync-reset flop (reset mux on D); assert reset with the clock stalled.
2. Observe: the async flop clears immediately; the sync flop stays X (no edge to sample reset).
3. Change: advance the clock while reset is asserted.
4. Expect: the sync flop now clears at the edge. Then flip the reset polarity and watch "reset" hold the wrong level — proving style and polarity both matter.

Any free Verilog simulator shows async vs sync reset behaviour. No paid tool required.

Interview Perspective

• Weak: "Reset just sets the flops to zero."
• Good: "Async reset acts immediately via the reset pin; sync reset acts at the next clock edge via the data path."
• Senior: "At the gate level, an async flop has an RN pin and clears immediately; a sync reset is folded into D and clears at the next edge. I read the netlist to know which, match stimulus and polarity, and remember that correct sync behaviour can look like a 'broken' reset. Async release timing (recovery/removal) is a separate concern."

9. Interview / Review Questions

10. Key Takeaways

• Reset brings the netlist out of X (flops power up unknown, 2.6); the style determines when.
• Asynchronous reset acts immediately via the flop's dedicated reset pin (RN) — the UDP reset row fires regardless of the clock (2.3); cell e.g. DFFRX1.
• Synchronous reset acts only at a clock edge, folded into the D logic (a reset mux) — takes effect at the next edge.
• Polarity matters — standard cells often use active-low reset (RN): rst_n = 0 asserts.
• Read the netlist to know the style (RN pin vs D-mux) and match stimulus/polarity; correct sync behaviour can look 'broken'. (Async release timing is 7.3; GLS stays dynamic, STA signs off, 0.3.) Next: 7.2 — uninitialised flops & the startup problem.

Quick Revision

Reset brings flops out of X. Async = immediate via the RN pin (UDP reset row, no clock needed; DFFRX1). Sync = at the clock edge, folded into D (reset mux). Polarity: active-low RN, rst_n = 0 asserts. Read the netlist (RN pin vs D-mux); match stimulus/polarity; sync reset needs a clock edge (not broken). Release timing → 7.3. Next: 7.2 — uninitialised flops & the startup problem.