GLS · Chapter 0 · Foundation

A Mental Model for Reading Gate-Level Sims

Chapter 0 closes with a repeatable procedure for reading any gate-level simulation, the way an experienced engineer does. Beginners open a gate-level waveform, see a screen full of X and unfamiliar cell names, and freeze. A fixed five-step method makes the same waveform tractable. First, know the timing mode, because you cannot interpret a signal without it. Second, go to the first point of divergence rather than chasing downstream symptoms, since a screen of X is usually one source spreading. Third, classify the failure by category, such as X at init or reset, an X-optimism escape, timing, a tool-flow mismatch, or CDC and scan. Fourth, ask whether it is a mode artifact like a zero-delay race or a genuine bug. Fifth, trace to the source, not the symptom. This lesson applies the method to a waveform flooded with X that reduces to one uninitialised flop.

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Chapter 0 · Section 0.5 · GLS Foundations

Project thread — the D flip-flop's runs from 0.1–0.4 become waveforms and logs here, read with one procedure. The X from 0.2 and the modes from 0.4 are the things this procedure names — and it is the bridge into Chapter 1.

1. Why Should I Learn This?

A gate-level simulation gives you more signals than you can read and fewer familiar names than you are used to — thousands of cell instances, an ocean of X, and no tidy RTL structure. Without a procedure, you drown: you chase the loudest symptom, mistake a mode artifact for a bug, and burn a day. With a procedure, a gate sim becomes tractable — you know exactly what to look at first, how to classify it, and how to reach the source. This mental model is the difference between staring at a gate sim and reading one.

It is also the capstone of Chapter 0: it fuses the four foundations (why, what, where, modes) into how you actually work, and it is the template every later debugging chapter (X-prop, reset, timing, CDC, scan) specialises.

2. Industry Story — a screen of X that was one flop

A junior engineer is handed a failing gate-level simulation: the waveform is a wall of X — dozens of signals unknown across a datapath, the whole block looks broken. They start at the output (where the failure was reported) and work backward signal by signal, each X leading to another X, for most of a day, overwhelmed by the sheer count.

A senior engineer glances at it and asks one question: "where is the first X, at time zero, and what mode is this?" It is a zero-delay post-synthesis run, and reading from t=0 shows a single flop coming up X and never clearing — and every other X on the screen is downstream of that one, fanning out through the combinational logic it feeds. The 'wall of X' was one uninitialised flop (a reset-coverage bug) spreading. The fix was to that one flop; the dozens of downstream X vanished at once. The junior had been debugging symptoms (downstream X); the senior debugged the first divergence (the source). The post-mortem lesson: a gate-level sim flooded with X is almost always one source spreading, so you read from time zero, find the first divergence, and trace that to its source — never chase the downstream symptoms; and you cannot interpret any of it without first knowing the timing mode. A fixed reading procedure turns an overwhelming gate sim into a single root cause.

3. Concept — the five-step reading procedure

Read any gate-level simulation with a fixed procedure — it unifies the whole chapter:

1. Know the mode. Is this zero-delay, unit-delay, or full-timing (0.4)? You cannot interpret a value, an ordering, or a race without it — a signal that is 'wrong' in zero-delay may be a race, not a bug.
2. Go to the first divergence. Read from time zero. Find where the sim first departs from expectation — the first X, the first mismatch — not the reported downstream symptom. A screen of X is usually one source spreading; the first X is the lead.
3. Classify by catch category (0.2). Is the first divergence: X at init/reset? an X-optimism escape (RTL hid it, gates exposed it)? a timing effect? a tool-flow mismatch? CDC/scan behaviour? The category tells you which chapter's method applies.
4. Ask: mode artifact vs real bug (0.4). Could this be a zero-delay race or X-pessimism (the netlist being over-pessimistic about X) — an artifact of the mode — rather than a genuine defect? Rule it out (re-run with ordering/timing) before concluding.
5. Trace to source, not symptom. Follow the first divergence back to the state element or construct that produced it, and fix that — the downstream symptoms clear on their own.

The unifying model (from 0.2): the netlist is a faithful narrator, so read it from the beginning and find the first thing it could not resolve. Here is the procedure as a flow:

Figure 1 — a repeatable procedure for reading any gate-level sim. (1) KNOW THE MODE (zero/unit/full) — you cannot interpret a signal or a race without it. (2) GO TO THE FIRST DIVERGENCE — read from t=0, find where it FIRST goes wrong, not the downstream symptoms (a screen of X is usually ONE source spreading). (3) CLASSIFY by catch category — X-init/reset, X-optimism escape, timing, tool-flow, CDC/scan. (4) ASK MODE-ARTIFACT vs REAL BUG — a zero-delay race or X-pessimism is an artifact, not a defect; rule it out. (5) TRACE TO SOURCE, not symptom — fix the state element/construct that produced the first divergence, and the downstream clears.

4. Mental Model — read the netlist like a faithful narrator, from the beginning

Mental Model — a gate sim is a faithful narrator telling a story from t=0; find the first sentence that goes wrong, not the last

A gate-level simulation is the faithful narrator (0.2) telling the story of your design from time zero. When the story goes wrong, you do not analyse the chaotic final scene — you find the first sentence that broke, because everything after it is consequence.

Debugging a gate sim is like finding where a story first went off the rails. The ending (the reported failure, the wall of X at the output) is loud and confusing — but it is downstream of a single earlier moment where the narrator first could not continue truthfully (the first X, the first mismatch). An inexperienced reader argues with the ending; an experienced one rewinds to the first broken sentence, because the narrator is faithful — it did not invent the chaos, it propagated one early indeterminacy. So you read from the beginning, in the edition you were handed (the mode — a sketch, storyboard, or film, 0.4), find the first place the story diverges, and ask: what kind of break is this (which catch category, 0.2), and is it even a real break or a quirk of this edition (a zero-delay race, X-pessimism)? Only then do you trace the first break to its cause — the character who was never introduced (the uninitialised flop), the scene the editor cut (a construct that vanished in synthesis), the cue that arrived late (a timing effect). Fix the cause, and the chaotic ending rewrites itself. This is the whole discipline of GLS in one habit: the netlist tells the truth from t=0, so read from t=0, find the first divergence, classify it, rule out edition-quirks, and trace to source. Every later chapter — X-prop, reset, timing, CDC, scan — is this same habit, specialised to one category of first-divergence.

Two anchors:

The first divergence is the bug; the rest is consequence. Read from t=0, fix the first X/mismatch's source — never chase the downstream flood.
Interpret in the light of the mode, and rule out mode artifacts. A 'wrong' value or race may be a zero-delay/X-pessimism artifact — know the mode (0.4) and rule out artifact before concluding a bug.

5. Working Example — applying the procedure to an X-flooded sim

You are handed a failing gate sim: the datapath output is X and the waveform is full of X. Apply the five steps.

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Snippet

// The scene: a datapath whose output is X. Dozens of intermediate signals are also X.
// Instead of reading the OUTPUT, apply the procedure.
//
// STEP 1 — KNOW THE MODE:  this is a POST-SYNTHESIS, ZERO-DELAY run (function/X check). (0.4)
// STEP 2 — FIRST DIVERGENCE: read from t=0. The FIRST X appears at a single flop U_state,
//          which comes up X and never clears. Every other X is LATER and DOWNSTREAM of it.
// STEP 3 — CLASSIFY: first X at t=0 on a flop that never clears -> X at init / RESET COVERAGE. (0.2)
// STEP 4 — ARTIFACT vs REAL: zero-delay race? No (it is stable across runs, at t=0). X-pessimism?
//          No (it is a genuinely uninitialised flop). -> a REAL bug. (0.4)
// STEP 5 — TRACE TO SOURCE: U_state is not on the reset net. Fix THAT flop's reset. (source, not symptom)

A representative gate view of the source — the single flop that is not reset — versus the many it feeds:

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Snippet

// The SOURCE: one flop missing its reset connection (conceptual).
DFFX1  U_state (.D(next), .CK(clk), .Q(state));              // NO reset pin driven -> Q starts X, never clears
// The SYMPTOMS: the combinational cone downstream, all X because 'state' is X.
MUX2X1 U_dp0 (.A(x0), .B(x1), .S(state), .Y(y0));            // S=X -> Y=X  (downstream symptom)
AND2X1 U_dp1 (.A(y0),  .B(en),           .Y(y1));            // X in -> X out (downstream symptom)
// ... dozens more, ALL X because of the one un-reset flop upstream.

The expected log, read the procedure's way — first divergence first:

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Snippet

# Read from t=0. The FIRST X is the lead; the rest are consequences.
t=0  U_state.Q = x        <- FIRST DIVERGENCE (source): un-reset flop, never clears
t=0  U_dp0.Y   = x        <- downstream of U_state.Q (symptom)
t=0  U_dp1.Y   = x        <- downstream (symptom)
t=0  ... dozens of X ...  <- all consequences of the ONE source
# After fixing U_state's reset and re-running:
t=7  U_state.Q = 0        <- source now resets -> the entire downstream X flood clears

The 'wall of X' was one uninitialised flop spreading. The procedure took you past the symptoms to the source in five steps: mode → first X → classify (init/reset) → real (not artifact) → fix the source. That is how you read any gate sim.

6. Debugging Session — chasing symptoms instead of the first divergence

A gate sim flooded with X is 'debugged' from the output backward, one symptom at a time, for hours — when the procedure (first divergence, from t=0) reduces it to one uninitialised flop

FIRST DIVERGENCE, NOT DOWNSTREAM SYMPTOMS

Symptom

A failing gate-level simulation shows a wall of X — dozens of unknown signals across a datapath — with the failure reported at the output. The natural but wrong instinct is to start at the output and trace backward, signal by signal, each X leading to another. It is slow, overwhelming, and produces no root cause: every signal you examine is 'X because its input is X,' endlessly, because you are reading symptoms.

Root Cause

The debugging method is the problem, not (yet) the design. A gate sim flooded with X is almost always one source spreading — a single early indeterminacy propagating through the combinational cone it feeds — so most of the X on the screen are consequences, and reading from the output backward means wading through symptoms. Applying the procedure instead: (1) Know the mode — a zero-delay post-synthesis run, so a stable X at t=0 is meaningful (not a race). (2) Go to the first divergence — read from t=0, and the first X is a single flop that comes up X and never clears; every other X is later and downstream. (3) Classify — first X at t=0 on a flop that never clears is X-at-init / reset coverage (0.2). (4) Artifact vs real — not a race (stable, at t=0), not X-pessimism (genuinely un-reset) → a real bug. (5) Trace to source — that flop is not on the reset net. The dozens of downstream X were never separate bugs; they were the one un-reset flop's X fanning out. Chasing them backward from the output was chasing symptoms of a single source.

Fix

Fix the source — bring the one uninitialised flop onto the reset (or fix its reset sequencing) so it comes up known — and re-run; the entire downstream X flood clears at once, because it was all consequence. The lesson the failure teaches, and the capstone of Chapter 0: read a gate sim with a fixed procedure — know the mode, go to the first divergence from t=0 (not the downstream symptoms), classify it by catch category, rule out mode artifacts (races, X-pessimism), and trace to source — because a flood of X is usually one source spreading, and the first divergence is the bug while the rest is consequence. Every later debugging chapter specialises this one habit; master it here on the simplest case (a flood of X) and you can read any gate-level simulation.

7. Common Mistakes

Reading from the output backward, chasing symptoms. A flood of X is usually one source spreading — go to the first divergence from t=0, not the loudest downstream symptom.
Interpreting a signal without knowing the mode. A 'wrong' value or non-determinism in zero-delay may be a race, not a bug — always establish the mode first (0.4).
Concluding "bug" before ruling out mode artifacts. Zero-delay races and X-pessimism are artifacts; rule them out (re-run with ordering/timing) before editing the design (0.4).
Not classifying the first divergence. The category (X-init, X-optimism, timing, tool-flow, CDC/scan) tells you which method applies — skipping it means debugging blind (0.2).
Fixing a symptom, not the source. Suppressing a downstream X leaves the source producing more — trace the first divergence to the state element/construct that made it.

8. Industry Best Practices

Run the fixed procedure on every gate sim. Mode → first divergence → classify → artifact-vs-real → trace to source — it turns an overwhelming sim into one root cause.
Always establish the timing mode first. You cannot interpret a value, an ordering, or a race without knowing zero/unit/full (0.4).
Debug the first divergence, never the downstream flood. The first X/mismatch from t=0 is the lead; the rest is consequence.
Rule out mode artifacts before touching the design. A race or X-pessimism is not a defect — re-run with ordering/timing to confirm real-vs-artifact.
Trace to source and fix once. Fixing the state element/construct behind the first divergence clears the downstream symptoms together.

9. Interview / Review Questions

10. Key Takeaways

Read any gate-level simulation with a fixed five-step procedure — it turns an overwhelming sim into a single root cause and unifies all of Chapter 0.
1. Know the mode (zero/unit/full, 0.4) — you cannot interpret a value or a race without it. 2. Go to the first divergence — read from t=0, find the first X/mismatch, not the downstream symptoms.
3. Classify by catch category (0.2) — X-init/reset, X-optimism escape, timing, tool-flow, CDC/scan — the category chooses the method. 4. Ask artifact vs real (0.4) — rule out a zero-delay race or X-pessimism before concluding a bug.
5. Trace to source, not symptom — a flood of X is usually one source spreading, so fix the state element/construct behind the first divergence and the downstream clears on its own.
The unifying model: the netlist is a faithful narrator telling the story from t=0 — read from the beginning, find the first divergence, classify it, confirm it is real, trace to source. Chapter 0 gave you why, what, where, modes, and now how to read — Chapter 1 begins the deep work: exactly how netlist behaviour diverges from RTL, starting with the D flip-flop.

Senior Engineer Thinking

Beginner: "The whole block is full of X — dozens of bugs."
Senior: "A flood of X is usually one source spreading. What mode am I in, and where is the first X at t=0? Fix that one source and the rest clears — the fiftieth X is a symptom, not a bug."

The senior debugs the first divergence, not the loudest downstream symptom — the single habit every later GLS debug chapter specialises.

Silicon Impact

If you debug symptoms and never reach the source, the one uninitialised flop (or undefined control) behind the flood ships. That single unfixed source is a real power-up / reset defect: intermittent boot hangs, field returns, and a debug bill that grows with how far downstream you chased symptoms instead of rewinding to t=0. The procedure is cheap; the escape is not.

Engineering Checklist

Established the timing mode before interpreting any signal.
Read from t=0 to the first divergence — not the downstream flood.
Classified the first divergence by catch category.
Ruled out mode artifacts (zero-delay race, X-pessimism) before concluding a bug.
Traced to the source and fixed once — confirmed the downstream cleared.

Quick Revision

How to read any gate sim: mode → first divergence (t=0) → classify → artifact-vs-real → trace to source. A flood of X is one source spreading; the first divergence is the bug, the rest is consequence. This closes Chapter 0 — next: Chapter 1 digs into exactly how netlist behaviour diverges from RTL, starting with this same flip-flop.