Working Example: A CDC Glitch Only GLS Caught

Chapter 9 · Section 9.5 · CDC & Asynchronous Behaviour in GLS

Project thread — the mini-SoC's inter-domain control is exactly where reconvergence glitches hide. This capstone closes the CDC chapter; Chapter 10 takes low-power (power domains, isolation, retention) as its whole subject.

1. Why Should I Learn This?

This is the chapter's thesis made concrete: GLS catches real-delay CDC bugs that static CDC and RTL cannot.

• A reconvergence glitch passes static CDC (structure OK) and RTL (zero-delay).
• GLS with real delays reveals it — the complementary role (9.1).
• The fix is a design principle (synchronize one signal, not reconverged bits).

It integrates 9.1–9.4 on one bug and closes the chapter.

2. Real Silicon Story — the crossing that passed every static check and still failed

A crossing passed static CDC (both bits synchronized) and passed RTL simulation — yet failed intermittently in silicon.

Two related control bits were synchronized independently and reconverged in an AND in the receive domain. Their synchronizers resolved on slightly different edges with different real delays, so the AND output glitched, and a downstream flop captured the glitch. Static CDC (topology) and zero-delay RTL (no arrival skew) were blind to it; a GLS run with real delays showed the glitch immediately.

Lesson: independently-synchronized bits that reconverge can glitch under real delays — invisible to static CDC and RTL, visible to GLS. Synchronize a single signal.

3. Concept — reconvergence, and why only GLS sees it

The bug — reconvergence of independently-synchronized bits:

• Two related bits each cross via their own synchronizer (9.3).
• The two synchronizers can resolve on different edges and arrive with different real delays.
• They reconverge through combinational logic (e.g. AND/decode) → the combined signal glitches.
• A receive flop samples the glitch → wrong value / X.

Why each tool sees or misses it:

• Static CDC — checks structure: both bits are synchronized → passes (blind to real-delay reconvergence).
• RTL (zero-delay) — no arrival skew, so the reconverged signal doesn't glitch → passes.
• GLS (real delays) — the skewed arrivals glitch the reconverged signal → caught (9.1).

Applying the chapter:

• 9.1 — GLS reveals real-delay behaviour static misses (this bug).
• 9.2 — it's a real glitch, not metastability (don't mis-classify).
• 9.3 — the per-bit synchronizers were fine; the problem is after them.
• 9.4 — the principle: cross a single value (gray-coded if multi-bit), don't reconverge independently-synchronized bits.

The fix:

• Synchronize a single signal — combine before crossing, cross one synchronized bit (or gray-coded value), so there's nothing to reconverge in the receive domain.
• Or re-time so no reconvergence glitch is sampled.

Scope (accuracy):

• GLS complements static CDC — it catches real-delay effects, not structure or metastability (9.1/9.2). STA signs off timing (0.3).

4. Mental Model — two clocks synchronized separately drift, and their AND flickers

Imagine two people setting their watches from two different radio signals (independent synchronizers), then agreeing to act when both watches read 12:00 (the reconverging AND).

• Because they synced separately, their watches tick slightly apart (different real delays).
• For a brief instant, one reads 12:00 and the other 11:59 — the "both agree" signal flickers (glitch).
• Someone glancing at exactly that instant (the receive flop) sees a false "go" — a wrong action.
• In zero-delay RTL, both watches are perfectly in sync (no drift) → no flicker. Static CDC only checked that each watch was set from a radio (structure) → passed.
• Fix: have one person set one watch and tell the other — a single synchronized source, nothing to reconverge.

Only the real-delay view (GLS) shows the flicker.

5. Working Example — the reconvergence bug and the fix

The buggy reconvergence and the single-signal fix (representative):

// BUG — two related bits synchronized INDEPENDENTLY, then reconverged in the receive domain
sync2 u_s0 (.clk(clk_b), .d(a0), .q(a0_sync));   // bit0 synchronizer (9.3)
sync2 u_s1 (.clk(clk_b), .d(a1), .q(a1_sync));   // bit1 synchronizer (9.3)
assign go = a0_sync & a1_sync;                    // RECONVERGE: skewed arrivals -> GLITCH
always_ff @(posedge clk_b) go_q <= go;            // samples the glitch -> wrong / X

// FIX — combine BEFORE crossing, synchronize a SINGLE signal (nothing to reconverge)
assign go_a = a0 & a1;                             // combine in the SOURCE domain
sync2 u_sg (.clk(clk_b), .d(go_a), .q(go_sync));   // cross ONE synchronized bit
always_ff @(posedge clk_b) go_q <= go_sync;        // clean -- no reconvergence glitch

# Why each tool sees it or not (tool-neutral):
#   static CDC:  a0, a1 both synchronized -> STRUCTURE OK -> PASS (blind to real-delay reconvergence)
#   RTL (0-delay): a0_sync, a1_sync arrive together -> no glitch -> PASS
#   GLS (real delays): a0_sync, a1_sync skew -> 'go' GLITCHES -> receive flop samples it -> CAUGHT

Practical context (representative, tool-neutral):

# Root-cause a CDC reconvergence glitch (applying Ch9, tool-neutral):
#   9.1: GLS (real delays) shows a glitch static CDC / RTL missed
#   9.2: it's a REAL glitch, NOT metastability (don't mis-classify the X)
#   9.3: the per-bit synchronizers are fine -- the bug is AFTER them
#   9.4: principle -- cross a SINGLE synchronized signal; don't reconverge independent bits
#   fix: combine before crossing (synchronize one bit) OR re-time so no glitch is sampled

The reconvergence glitch (buggy) vs the single-signal fix, as a real waveform:

6. Debugging Session — a crossing that passed static CDC and RTL, caught by GLS

7. Common Mistakes

• Reconverging independently-synchronized bits. Skewed arrivals glitch under real delays.
• Trusting static CDC alone. It checks structure, not real-delay reconvergence.
• Trusting zero-delay RTL for CDC. No arrival skew → no glitch shown.
• Mis-classifying the glitch as metastability. It's a real reconvergence glitch (9.2).
• Not synchronizing a single signal. Combine before crossing; cross one bit.

8. Industry Best Practices

• Synchronize a single signal — combine before crossing; don't reconverge independent bits.
• Use GLS (real delays) for CDC alongside static CDC — complementary (9.1).
• For multi-bit, use gray code / async FIFO (9.4).
• Distinguish a real glitch from metastability (9.2).
• Re-time if reconvergence is unavoidable, so no glitch is sampled.

Senior Engineer Thinking

• Beginner: "Static CDC and RTL passed, so the crossing is fine."
• Senior: "Are independently-synchronized bits reconverging? Static CDC checks structure, RTL is zero-delay — neither shows the real-delay glitch. GLS does. I'll synchronize a single signal so there's nothing to reconverge."

The senior treats reconvergence of synchronized bits as a real-delay hazard GLS catches, and crosses a single signal.

Silicon Impact

This capstone is the chapter's thesis in one bug: a crossing that passes every static check and RTL yet fails in silicon — the most dangerous kind, because it evades the tools teams trust most. A reconvergence glitch from independently-synchronized bits is a real-delay phenomenon: static CDC (structure) and zero-delay RTL are constitutionally blind to it, so without GLS it ships and causes intermittent, timing-sensitive silicon failures (0.3). GLS with real delays is exactly the tool that catches it — the complementary role of 9.1 made concrete. The fix is a robust design principle (synchronize a single signal), and the debugging skill is recognising a real glitch, not metastability (9.2). This is why GLS earns its place in CDC verification alongside static CDC and MTBF.

Engineering Checklist

• Checked for reconvergence of independently-synchronized bits.
• Synchronized a single combined signal (combine before crossing).
• Used GLS (real delays) alongside static CDC (9.1).
• Classified the glitch as real (not metastability, 9.2).
• For multi-bit, used gray code / async FIFO (9.4).

Try Yourself

1. Synchronize two related bits independently and reconverge them (go = a0_sync & a1_sync) in the receive domain; run with real delays.
2. Observe: go glitches from the skewed arrivals, and the receive flop samples it — a GLS-only bug (RTL/zero-delay is clean).
3. Change: combine before crossing (go_a = a0 & a1) and synchronize the single go_a.
4. Expect: no reconvergence, no glitch — the crossing is clean. Confirm static CDC passed the buggy version (structure OK) to see why GLS was essential.

Any free Verilog simulator with two async clocks and SDF delays reproduces the reconvergence glitch. No paid tool required.

Interview Perspective

• Weak: "If static CDC passes, the crossing is safe."
• Good: "Independently-synchronized bits reconverging can glitch under real delays; synchronize a single signal instead."
• Senior: "Static CDC checks structure and RTL is zero-delay, so both miss a reconvergence glitch — two synchronizers resolving on different edges with different real delays make their AND glitch, sampled by a receive flop. GLS with real delays catches it. I synchronize a single combined signal so there's nothing to reconverge — and I classify it as a real glitch, not metastability."

9. Interview / Review Questions

10. Key Takeaways

• A reconvergence CDC glitch happens when independently-synchronized bits (each fine on its own, 9.3) reconverge through combinational logic and their skewed real-delay arrivals glitch the combined signal, which a receive flop samples.
• Static CDC (structure) and zero-delay RTL (no arrival skew) miss it; only GLS with real delays catches it — the complementary role of 9.1 made concrete.
• It is a real glitch, not metastability (9.2) — don't mis-classify the X.
• Fix: synchronize a single signal — combine the bits in the source domain before crossing, cross one bit (gray-code / async FIFO for multi-bit, 9.4) — so there's nothing to reconverge.
• This is the chapter's thesis: GLS complements static CDC and MTBF by catching real-delay CDC behaviour they cannot see (dynamic; STA signs off timing, 0.3). This closes Chapter 9; next, Chapter 10 takes Low-Power GLS.

Quick Revision

Reconvergence glitch: independently-synchronized bits (9.3) reconverge → skewed real-delay arrivals glitch the combined signal → receive flop samples it. Static CDC (structure) + zero-delay RTL MISS it; GLS (real delays) CATCHES it (9.1). It's a real glitch, not metastability (9.2). Fix: synchronize a SINGLE signal (combine before crossing; gray/FIFO for multi-bit, 9.4). GLS complements static CDC/MTBF. Chapter 9 complete; next: Chapter 10 — Low-Power GLS.