DFT · Chapter 1 · Manufacturing Test Mindset

Wafer, Package & System-Level Test

A chip is not tested once but at several insertions, each catching defects the previous stage could not. Wafer sort probes the bare die while it is still on the wafer and culls bad dies early, before you spend money dicing and packaging them, producing a wafer map. Final or package test runs after dicing and packaging and catches assembly defects like broken bond wires and bad solder that did not exist at the wafer. System-level test runs the part in a near-real system and catches subtle defects that structural test misses, such as marginal timing. Burn-in stresses parts to precipitate infant mortality so weak dies fail in the factory instead of the field. The governing principle is that earlier insertions are cheaper to cull at, and each later stage exists because new defects appear or hide.

Foundation13 min readDFTWafer SortPackage TestSystem-Level TestBurn-In

Chapter 1 · Section 1.3 · Manufacturing Test Mindset

Project thread — the 4-bit counter die, followed through every test insertion from bare wafer to shipped part.

1. Why Should I Learn This?

A chip is tested at several insertions, and knowing which stage catches what is core test-engineering literacy:

Wafer sort — probe the bare die on the wafer; cull early (before packaging cost). → wafer map.
Final / package test — after dicing + packaging; catches assembly defects (bond/solder).
System-level test (SLT) — run in a near-real system; catches what structural test misses.
Burn-in — stress to precipitate infant mortality (weak parts fail in the factory, not the field).

Principle: earlier = cheaper to cull; each stage catches what the last couldn't.

2. Real Silicon Story — the die that passed wafer but failed final

A counter die passed wafer sort cleanly — every structural pattern good. It was diced, packaged, and sent to final test, where it failed.

Was the wafer test wrong? No. The package step introduced a new defect — a marginal bond wire that didn't exist when the die was bare silicon on the wafer. Wafer sort couldn't have caught it; the defect wasn't there yet. That's the entire reason final test exists as a separate insertion: packaging and assembly create defects of their own, so you must re-test after packaging.

A different die passed both structural insertions but failed system-level test — a marginal timing interaction that only showed up when the part ran in a real board. Lesson: no single insertion catches everything. Earlier stages cull cheaply; later stages catch what earlier ones can't see — new defects (packaging) or hidden ones (system-only).

3. Concept — the test insertions and why each exists

Wafer sort (probe / wafer test):

Runs on the bare die, still on the wafer, contacted by a probe card.
Applies mostly structural tests (scan/ATPG) — the same DFT this course builds.
Purpose: cull bad dies early — you don't want to pay to dice and package a die you already know is bad.
Artifact: a wafer map / bin map — a grid marking each die's pass/fail (and bin).

Final test (package test):

Runs on the packaged part, after dicing and assembly.
Catches package/assembly defects — bond wires, solder bumps, package cracks — that didn't exist at wafer.
Adds some functional / at-speed test on top of structural.

System-level test (SLT):

Runs the part in a near-real system/board, like the end application.
Catches subtle defects structural test misses — marginal timing, system interactions — the quality tail.
Higher cost per part, so used where quality demands justify it (or on the population that needs it).

Burn-in:

Applies stress (elevated voltage and temperature over time).
Precipitates infant mortality — weak dies that would fail early in the field are made to fail in the factory.

The governing principle — earlier is cheaper, each stage catches what the last couldn't:

Cost to discard rises at each stage (bare die < packaged part < system). So cull as early as possible.
But new defects appear (packaging) and some hide (system-only) — so you can't collapse to one insertion.

Figure 1 — the silicon test flow across insertions (representative). A wafer of dies goes to WAFER SORT (probe the bare die, cull bad dies EARLY, produce a wafer map) -> good dies are DICED + PACKAGED (this step INTRODUCES new defects) -> FINAL / PACKAGE TEST (re-test the packaged part, catch bond/solder defects) -> SYSTEM-LEVEL TEST (run in a near-real system, catch what structural missed) -> BURN-IN (stress to precipitate infant mortality) -> SHIP. Earlier insertions are cheaper to cull at; each later stage exists because new defects appear or hide that the earlier one could not see.

4. Mental Model — quality gates on an assembly line

Picture a factory assembly line with inspection gates at several points, not just one at the end.

Wafer sort is the first gate, on raw parts — cheap to reject here, before you spend labor assembling them. You cull early so you don't add value to a part you'll scrap.
Assembly (dicing + packaging) is a manufacturing step that can cause its own defects — so there's a second gate right after it (final test) to catch what assembly broke.
System-level test is a functional test-drive — you don't just inspect the car's parts, you drive it around the block to catch problems that only appear in operation.
Burn-in is a stress test / shakedown — run it hot and hard so the parts that were going to fail early fail here, in your factory, not at the customer.

You inspect at every stage that can introduce or reveal a defect — and you reject as early as it's cheapest.

5. Working Example — the counter die through the insertions

Follow one counter die through the flow, and see the wafer map artifact:

Azvya Education Pvt. Ltd.VLSI Mentor

Snippet

# The counter die through the insertions — REPRESENTATIVE:
  1) WAFER SORT   : probe bare die -> structural (scan/ATPG) pass -> marked GOOD on the wafer map -> keep
  2) DICE+PACKAGE : sawn from wafer, bonded into a package  (<-- a NEW defect can appear here)
  3) FINAL TEST   : re-test packaged part -> catches a bond-wire open that wafer sort could NOT see (not there yet)
  4) SLT          : run in a near-real board -> catches a marginal timing interaction structural test missed
  5) BURN-IN      : stress at high V/T -> a weak die that would die early in the field fails HERE instead
  6) SHIP         : only dies that passed EVERY insertion

A representative wafer map / bin map, the wafer-sort artifact:

Azvya Education Pvt. Ltd.VLSI Mentor

Snippet

# Wafer map (bin map) — REPRESENTATIVE (each cell = one die; earlier cull = cheaper):
   . . 1 1 1 . .        1 = PASS (good die, keep -> package)
   . 1 1 1 1 1 .        2 = FAIL bin 2 (structural defect -> discard NOW, before packaging cost)
   1 1 1 2 1 1 1        . = edge / no die
   1 1 2 1 1 1 1        Yield here = (# of 1s) / (# of dies)  -> the fab's yield (1.2)
   . 1 1 1 1 1 .        Culling the 2s at WAFER SORT avoids paying to package known-bad dies.
   . . 1 1 1 . .

6. Industry Flow — what each insertion catches vs its cost

Each insertion trades cost for the defects only it can catch:

Figure 2 — what each test insertion catches and its relative cost-to-cull (representative). WAFER SORT: structural defects on the bare die -> cheapest to cull (before packaging). FINAL/PACKAGE: assembly defects (bond/solder) that appear during packaging -> costs a packaged part to discard. SLT: subtle/system-only defects structural test misses -> higher cost, catches the quality tail. BURN-IN: infant-mortality (weak) parts -> stress cost. Principle: cull as EARLY as possible (cheapest), but keep later stages because they catch defects the earlier ones could not.

7. Debugging Session — a defect that passed wafer but failed later

A die passes wafer sort but fails final test (or SLT), and someone concludes wafer sort is broken; in fact packaging INTRODUCED a new defect (bond/solder) that did not exist at the wafer, or the defect only manifests in a running system -- which is exactly why test happens at multiple insertions and cannot be collapsed to one stage

EACH INSERTION CATCHES WHAT THE PREVIOUS COULD NOT

Symptom

A counter die passed wafer sort but failed final test (or passed both structural insertions and failed SLT). Someone concludes the earlier test 'missed it' and wants to tighten wafer sort or skip final to save cost.

Root Cause

Later insertions catch defects the earlier one could not see — because the defect either did not exist yet or only manifests in a system. A die that passes wafer sort then fails final most often has a packaging/assembly defect — a marginal bond wire, a bad solder bump, a package crack — that was physically not present when the die was bare silicon on the wafer. Wafer sort didn't 'miss' it; there was nothing to catch — the defect was created by the packaging step that happens after wafer sort. Similarly, a die that passes both structural insertions but fails SLT typically has a subtle, system-only defect — a marginal timing interaction that structural scan/ATPG patterns don't exercise but a real running system does. Two wrong instincts: (1) 'wafer sort is broken' — no, it correctly tested the die as it existed then; (2) 'skip final/SLT to save cost' — that would let assembly defects and system-only defects escape straight to the customer. The whole point of multiple insertions is that new defects appear (packaging) and some hide (system-only), so no single stage can catch everything.

Fix

Keep the insertions — but assign each the defects only it can catch, and cull as early as possible. Use wafer sort for cheap, early structural culling (high-coverage scan/ATPG on the bare die → discard bad dies before paying to package them). Use final/package test to re-test after assembly and catch packaging defects that wafer sort couldn't (they didn't exist yet). Use SLT where quality demands justify its cost, to catch the system-only tail that structural test misses. Use burn-in to precipitate infant mortality so weak parts fail in the factory, not the field. The mental model to lock in: a chip is tested at several insertions — wafer sort (bare die, cull early, cheapest), final/package test (catch assembly defects that packaging introduced), system-level test (catch subtle defects structural test misses), and burn-in (stress out infant mortality) — because earlier stages are cheaper to cull at while each later stage exists to catch defects that appear or hide beyond the earlier one's reach. And note the through-line: wafer sort's power comes from structural DFT — the scan/ATPG this course builds is the cheap, early, high-coverage backbone that makes the earliest, cheapest cull possible. (Test time/cost per insertion is 1.4; DPPM across the flow is 1.5.)

8. Common Mistakes

Assuming one test insertion is enough. Packaging introduces defects; some defects only show in a system.
Blaming wafer sort for a final-test fail. The packaging step likely created the defect afterward.
Skipping early culling. Not testing at wafer sort means paying to package known-bad dies.
Treating SLT as redundant. SLT catches the structural-blind tail — marginal timing, system interactions.
Confusing burn-in with functional test. Burn-in is stress for infant mortality, not a coverage test.

9. Industry Best Practices

Cull as early as it's cheapest — strong structural test at wafer sort discards bad dies pre-packaging.
Re-test after packaging — final test catches assembly defects the wafer couldn't.
Use SLT for the quality tail where field quality demands it.
Use burn-in / stress to precipitate infant mortality on reliability-critical parts.
Analyze the wafer map spatially — clusters/edge fails distinguish process from design issues.

10. Senior Engineer Thinking

Beginner: "It passed wafer sort but failed final — wafer sort is unreliable."
Senior: "Packaging happens between those insertions and creates its own defects — a bond wire, a solder bump. Wafer sort tested the die as it was then; final catches what assembly broke. Each insertion has a job: cull early where it's cheap, catch new defects after packaging, and catch the system-only tail in SLT. I never collapse them into one."

The senior sees insertions as a defense in depth, each catching what the others structurally cannot.

11. Silicon Impact

Where you test decides how much a bad die costs you and which defects you catch at all. Culling at wafer sort — enabled by the cheap, high-coverage structural DFT this course builds — means you never pay to package a known-bad die, and that early cull is the highest-leverage cost move in the whole flow (packaging and assembly are expensive; throwing away a bare die is nearly free). Final test exists because packaging is itself a defect source — skip it and assembly defects escape to customers. SLT buys the quality tail that structural test structurally cannot reach — the marginal, system-only failures — which is why safety- and reliability-critical products invest in it. Burn-in trades factory time for field reliability, catching infant mortality before the customer does. For an RTL/DFT engineer, the key realization is that the strength of your structural test directly sets how much you can cull early and cheaply — better testability (Chapters 3–6) pushes more defect detection to the cheapest insertion (wafer sort), shrinking how many defects have to be caught expensively downstream (or escape). Test insertions are defense in depth; DFT is what makes the cheapest layer strong.

12. Engineering Checklist

Placed strong structural test at wafer sort to cull bad dies before packaging.
Kept final test to catch assembly/package defects (bond, solder).
Used SLT where the quality tail (system-only defects) justifies the cost.
Used burn-in for infant mortality on reliability-critical parts.
Analyzed the wafer map spatially (clusters/edges → process vs design).

13. Try Yourself

Draw the wafer map for a lot of counters — mark a few structural fails (bin them at wafer sort).
Trace one good die forward: dice → package → final test. Introduce a bond-wire defect at packaging — show it can only be caught at final, not wafer.
Trace another die that passes structural but has a marginal timing issue — show it needs SLT to catch.
Compare cost-to-discard at each stage (bare die < packaged < system) and confirm culling early is cheapest.
Explain why skipping final test would let assembly defects escape.

The reasoning is tool-independent — a paper wafer map and the flow diagram suffice. The structural patterns behind wafer sort come from any ATPG flow (Chapters 5–6). No paid tool required.

14. Interview Perspective

Weak: "The chip gets tested at the factory."
Good: "It's tested at wafer, after packaging, and sometimes in a system, plus burn-in."
Senior: "Test happens at several insertions. Wafer sort probes the bare die and culls early, before packaging cost — it makes a wafer map. Final test re-tests the packaged part and catches assembly defects (bond/solder) that didn't exist at the wafer. SLT runs the part in a near-real system and catches subtle defects structural test misses. Burn-in stresses parts to precipitate infant mortality. The principle is cull as early as it's cheapest, but keep every stage because each catches defects the previous one couldn't — and strong structural DFT is what makes the earliest, cheapest cull possible."

15. Interview / Review Questions

16. Key Takeaways

A chip is tested at several insertions, each catching defects the previous one could not.
Wafer sort probes the bare die on the wafer and culls bad dies early — before dicing/packaging cost — producing a wafer map.
Final (package) test runs after dicing and packaging and catches assembly defects (bond wires, solder) that didn't exist at the wafer.
System-level test (SLT) runs the part in a near-real system and catches subtle defects structural test misses; burn-in applies stress to precipitate infant mortality.
Principle: cull as early as it's cheapest, but keep every stage because new defects appear (packaging) and some hide (system-only) — and strong structural DFT (this course) makes the cheapest, earliest cull possible. Next: 1.4 — why test time is money.

17. Quick Revision

Where test happens — insertions, defense in depth. WAFER SORT: probe the BARE die on the wafer, cull bad dies EARLY (before packaging cost) → wafer map. FINAL / PACKAGE: re-test the packaged part, catch ASSEMBLY defects (bond/solder) that didn't exist at wafer. SLT: run in a near-real system, catch subtle defects structural test MISSES. BURN-IN: stress → precipitate INFANT MORTALITY. Principle: cull as EARLY as it's cheapest; each later stage catches what the earlier COULDN'T. Structural DFT powers the cheapest cull. Next: 1.4 — why test time is money.