Improving Testability from RTL

Chapter 6 · Section 6.4 · Coverage & Signoff

Project thread — the FSM's one AU fault (5.6/6.3) — an unobservable illegal-state output — is fixed here with an observe point, closing its coverage.

1. Why Should I Learn This?

This is how you raise coverage — cheaply, at the cause, and ideally in RTL — instead of drowning in patterns.

• Control points fix controllability; observe points fix observability (the two halves, 5.2).
• SCOAP-guided insertion targets the hard nodes; the RTL engineer can design them in.
• Restructure hard logic, remove redundancy (kills RE, 2.5), wrap black boxes.
• A few test points beat thousands of patterns on the flat tail (5.3) — shift-left to RTL.

2. Real Silicon Story — a few test points vs a million patterns

A team was stuck on the flat tail of the coverage curve — the last 1.5% — and their plan was to generate more and more patterns. The pattern count ballooned (blowing the test-time budget, 1.4) while coverage barely moved: the tail faults were hard to control/observe, and more patterns can't create access the circuit doesn't offer.

A DFT engineer ran SCOAP and found the tail concentrated on a handful of high-CC/CO nodes. Inserting a few control and observe points at exactly those nodes — guided by the measures — lifted coverage past target immediately, and the pattern count dropped because the newly-accessible faults were easy to detect. A dozen test points did what a million patterns couldn't.

Lesson: the flat tail is a testability problem, not a pattern problem. A few well-placed test points (control for controllability, observe for observability) recover coverage cheaply — and doing it in RTL would have been cheaper still. Fix access, don't out-pattern it.

3. Factory Perspective — testability fixes through each lens

• What the test engineer sees: coverage rise with fewer patterns after a few test points — a better coverage and test-time (1.4) outcome than more patterns.
• What the yield engineer sees: that the hard-tail faults (now covered) were escape candidates — testability fixes directly cut escapes (DPPM, 1.5).
• What the RTL/DV engineer sees: that their logic's hard nodes (SCOAP-flagged), redundancy, and black boxes are the targets — designable-in (test points, restructure, wrappers) as a shift-left.
• What management cares about: that a few test points (small area/timing) beat thousands of patterns (test time) — a cost-efficient path to the coverage/DPPM target.

4. Concept — test points, restructuring, wrappers, testable RTL

Test points (the two halves, 5.2):

• Control point (controllability): a test-mode mux that forces a chosen value on a hard-to-control node during test → ATPG can justify through it.
• Observe point (observability): a scan flop that captures a hard-to-observe node → its value reaches a scan cell → ATPG can propagate to it.
• SCOAP-guided: high CC0/CC1 → control point; high CO → observe point. Tools auto-insert; RTL can design in.

Restructure hard-to-test logic:

• Break deep reconvergent fanout and huge fan-in (they make justification/propagation hard).
• Remove redundant logic → eliminates untestable RE faults (2.5) and their hidden-defect risk; redundancy added for timing/glitch may be removable or re-expressed.

Wrap black boxes:

• Put boundary registers (a wrapper) around untestable IP/analog/memory interfaces so boundary faults become controllable/observable → boundary scan (Chapter 10); use MBIST for the memory inside (Chapter 8).

Full scan + testable RTL (foundational):

• Ensure full scan and scan-ready RTL (4.1) — the baseline testability.
• Write testable RTL: avoid uninitialized X-sources, tie-offs that hide logic, and unobservable status bits — the constructs that create AU faults.

The economics (why test points win):

• Test points cost a little area and timing (like scan) — but they recover coverage cheaply: a few points at the tail beat thousands of patterns (5.3), which also cost test time (1.4).
• Shift-left: designing test points / testable RTL in RTL is cheaper than post-synthesis insertion.

5. Mental Model — adding a light switch and a window to a dark room

A hard-to-test node is a dark, sealed room you must inspect.

• If you can't turn the lights on (can't control it), you install a switch (a control point) — now you can set the room's state for inspection.
• If you can't see inside (can't observe it), you add a window (an observe point) — now you can read what's happening.
• If the room is a sealed vendor module (a black box), you build an inspection hatch around it (a wrapper) so you can at least check its doors (boundary).
• SCOAP is the building survey that tells you which rooms are dark (need a switch) vs windowless (need a window) — you don't add switches and windows everywhere, just where the survey flags.
• And it's far cheaper to add switches/windows during construction (RTL) than to knock through finished walls (post-synthesis) — and cheaper than hiring an army to search in the dark (piling on patterns).

Add a switch (control) or a window (observe) exactly where the survey (SCOAP) says — a few beat a million searchers.

6. Working Example — test points, and the FSM's observe point

Concise control/observe test points, and the FSM fix (SV shown; Verilog/VHDL parallel is identical in spirit):

// SystemVerilog — a CONTROL point and an OBSERVE point (test-mode only; mission behavior unchanged)
module test_points (
  input  logic clk,
  input  logic test_mode,          // 1 in test
  input  logic tp_ctrl_val,        // controllable value in test (from a scan cell)
  input  logic hard_to_control,    // functional signal, high SCOAP CC
  input  logic hard_to_observe,    // functional node, high SCOAP CO
  output logic node_out,
  output logic observe_q           // scan-observable tap
);
  // CONTROL POINT: in test, force a controllable value onto the hard node (restores controllability)
  assign node_out = test_mode ? tp_ctrl_val : hard_to_control;
  // OBSERVE POINT: a scan flop captures the hard-to-observe node (restores observability)
  always_ff @(posedge clk) observe_q <= hard_to_observe;   // observe_q is on a scan chain -> ATPG can read it
endmodule

# FSM AU fault fix (from 5.6/6.3) — REPRESENTATIVE, SIMPLIFIED, tool-neutral:
  Fault: an output defined only on an ILLEGAL state -> its effect can't propagate to a scan cell -> AU (unobservable)
  Diagnose (6.3): fails on OBSERVABILITY (propagation), not controllability
  FIX: add an OBSERVE POINT (a scan flop) on that output -> its value now reaches a scan cell
    -> ATPG loads the (illegal) state, captures, and OBSERVES the output -> fault becomes DETECTED
  RESULT: test coverage of the FSM closes (the lone AU -> DT). A control point would instead fix a can't-justify node.

# Economics: test points vs patterns on the FLAT TAIL (5.3) — REPRESENTATIVE:
  Flat tail = ~1.5% coverage, hard-to-control/observe faults
  Option A: +1,000,000 patterns -> coverage +0.2% (barely moves) + HUGE test time (1.4)  <- out-patterning fails
  Option B: +12 SCOAP-guided test points -> coverage +1.5% (past target) + pattern count DROPS (new faults are easy)
# A few well-placed test points beat a million patterns. Cheapest done in RTL (shift-left).

7. Industry Flow — SCOAP finds hard nodes, test points fix them

Testability improvement is a targeted, measured loop feeding signoff:

8. Debugging Session — the flat tail that swallowed patterns

9. Common Mistakes

• Out-patterning the flat tail. Hard-C/O faults need access, not more patterns — use test points.
• Adding test points everywhere. SCOAP-guide them to the hard nodes — area/timing cost otherwise.
• Confusing control and observe points. Control fixes controllability; observe fixes observability (5.2/6.3).
• Ignoring redundancy. Removing redundant logic kills RE faults (2.5) and their hidden-defect risk.
• Deferring to post-synthesis. RTL test points / testable RTL are cheaper — shift-left.

10. Industry Best Practices

• SCOAP-guide test points — control for high CC, observe for high CO, only where flagged.
• Prefer RTL / designed-in test points and testable RTL — shift-left.
• Restructure hard logic; remove redundancy (kills RE, 2.5).
• Wrap black boxes (boundary scan Ch10; MBIST Ch8) for their boundary/inside faults.
• Trade a little area/timing for a lot of coverage — a few points beat many patterns (test time, 1.4).

11. Senior Engineer Thinking

• Beginner: "Coverage is stuck on the last 1% — generate more patterns."
• Senior: "The tail is hard-to-control/observe faults — patterns can't reach them. I run SCOAP, add a few control/observe points at the flagged nodes, remove redundancy, and wrap black boxes. Coverage jumps and the pattern count drops. And I do it in RTL — cheaper than post-synthesis. Fix access, don't out-pattern it."

The senior fixes the flat tail with targeted test points (and testable RTL), not with more patterns.

12. Silicon Impact

Improving testability is the highest-leverage, most cost-efficient move in coverage closure, because it attacks the flat tail (5.3) — the hard-to-control/observe faults where patterns give vanishing returns — with access, which is what those faults actually lack. A control point restores controllability, an observe point restores observability, and SCOAP points you at exactly the nodes that need each — so a handful of well-placed test points routinely does what millions of patterns cannot, raising coverage and often lowering the pattern count (the new faults are easy), a double win on quality (DPPM, 1.5) and test cost (1.4). The same toolkit — restructuring reconvergent/high-fan-in logic, removing redundancy (which also kills RE faults and their hidden-defect risk, 2.5), and wrapping black boxes (boundary scan Chapter 10, MBIST Chapter 8) — closes the structural gaps that no ATPG effort can. The decisive economic and engineering insight is shift-left: testability is a design property, and building test points / testable RTL into the RTL is cheaper and more durable than post-synthesis insertion — and it's where the RTL/DV engineer has the most power, since the hard nodes, the redundancy, and the X-sources are theirs to fix at the source. For the project's FSM, this is the concrete close: its lone AU fault — an unobservable illegal-state output (6.3) — becomes detected with a single observe point, taking the block to its coverage target and readying it for signoff (6.5). The lasting lesson: when coverage stalls, don't out-pattern the tail — buy the access it's missing.

13. Engineering Checklist

• Used SCOAP to target hard nodes — control points (high CC), observe points (high CO).
• Designed test points / testable RTL in RTL where possible (shift-left).
• Restructured hard logic and removed redundancy (killed RE faults, 2.5).
• Wrapped black boxes (boundary scan Ch10 / MBIST Ch8) for boundary/inside faults.
• Verified coverage rose and pattern count held/dropped (test time, 1.4); mission behavior unchanged.

14. Try Yourself

1. For a high-CC node, add a control point (test-mode mux) and show ATPG can now justify through it.
2. For a high-CO node, add an observe point (scan flop) and show the effect now reaches a scan cell.
3. Fix the FSM's AU fault (unobservable illegal-state output) with an observe point → DT.
4. Show, on a flat tail, that +12 test points beat +1,000,000 patterns (coverage and test time).
5. Identify a piece of redundant logic and argue that removing it kills an RE fault (2.5) and a hidden-defect risk.

The techniques are tool-neutral; the SV test points are representative. Real SCOAP/insertion come from the DFT/ATPG tool. No paid tool required.

15. Interview Perspective

• Weak: "You add test points to improve coverage."
• Good: "Control points make hard nodes controllable and observe points make them observable, guided by SCOAP."
• Senior: "The flat tail of the coverage curve is hard-to-control/observe faults, and more patterns can't reach them — so I add test points: a control point (test-mode mux forcing a value) for a high-CC node → controllability, an observe point (scan flop tap) for a high-CO node → observability, SCOAP-guided to the exact nodes. I also restructure reconvergent/high-fan-in logic, remove redundancy (killing RE faults, 2.5), and wrap black boxes (boundary scan / MBIST). A few points raise coverage and drop the pattern count — cheaper than a million patterns and their test time — and I do it in RTL as a shift-left. Fix access, don't out-pattern it."

16. Interview / Review Questions

17. Key Takeaways

• Test points raise coverage by restoring the two halves of ATPG reasoning: a control point (test-mode mux) fixes controllability on a hard-to-control node; an observe point (scan flop tap) fixes observability on a hard-to-observe node — SCOAP-guided to the flagged nodes.
• Restructure hard-to-test logic (break reconvergent/high fan-in) and remove redundant logic — which eliminates untestable RE faults (2.5) and their hidden-defect risk.
• Wrap black-box interfaces (IP/analog/memory) with boundary registers so boundary faults become controllable/observable (boundary scan Ch10; MBIST for memory Ch8); ensure full scan + testable RTL (4.1).
• A few well-placed test points beat thousands of patterns on the flat tail (5.3): coverage rises and the pattern count often drops — better coverage and test time (1.4).
• Shift-left: designing test points / testable RTL in RTL is cheaper and more durable than post-synthesis insertion — testability is a design property, and the hard nodes/redundancy/X-sources are the RTL engineer's to fix. Next: 6.5 — coverage closure & signoff targets.

18. Quick Revision

Improving testability from RTL. The flat tail (5.3) = hard-to-control/observe faults → patterns can't reach them → add TEST POINTS: control point (test-mode mux forces a value → controllability, high SCOAP CC) + observe point (scan flop tap → observability, high SCOAP CO), SCOAP-guided to the flagged nodes. Also restructure reconvergent/high-fan-in logic, remove redundancy (kills RE faults 2.5 + hidden-defect risk), wrap black boxes (boundary scan Ch10 / MBIST Ch8). A few points beat thousands of patterns → coverage ↑ AND pattern count often ↓ (test time 1.4). Cheapest in RTL (shift-left). FSM's AU fault → one observe point → DT. Fix access, don't out-pattern it. Next: 6.5 — coverage closure & signoff targets.