Working Example: Test Control of a Clock-Gated Block

Chapter 11 · Section 11.5 · Test Modes & DFT Signals — chapter capstone

Project thread — the mini-SoC's clock-gated block is steered through all modes by its mode decoder; Chapter 12 constrains/times these modes in STA.

1. Why Should I Learn This?

This assembles every control from the chapter (and 2.3/3.4/4.4) on one block — the concrete picture of multi-mode test control.

• Functional: clock gate gates (power). Scan-shift: ICG test-enable forces clock on; SE=1; shift clock.
• Capture: SE settled; at-speed via OCC. Reset: gated off. Interfaces: isolated.
• All generated coherently by the mode decoder — mutually exclusive, glitch-free clocking.
• The whole chapter on one block — steered cleanly functional → scan-shift ↔ capture.

2. Real Silicon Story — one block, every control

A power-gated block had been a testability headache — clock gated so scan couldn't shift it (4.4), at-speed corruption from an unsettled scan-enable (3.4), an async reset that occasionally cleared loaded state (4.4), and X-masking from an un-isolated analog interface (11.4). Each had been patched ad-hoc, and the block still didn't test cleanly.

The fix was organized multi-mode control. A mode decoder (11.2) generated all the block's test controls coherently: the ICG test-enable (force clock on in scan/test, 4.4), scan-enable (balanced, settling before capture, 3.4/11.3), OCC for at-speed capture (2.3), reset gating (4.4), and isolation of the analog interface (11.4) — mutually exclusive modes with glitch-free clock selection (11.2). The block then stepped cleanly through functional → scan-shift ↔ capture, and coverage closed.

Lesson: a real block needs all the chapter's controls working together, organized by a mode decoder — clock-gate test-enable, scan-enable settle, OCC at-speed, reset gating, isolation — not ad-hoc patches. Get the mode control right and a power-gated block is fully testable.

3. Factory Perspective — the block's test control through each lens

• What the DFT engineer sees: the mode decoder driving the block's ICG test-enable, SE, OCC, reset gate, isolation — coherently, one mode at a time (11.1/11.2).
• What the CTS/physical engineer sees: SE distribution (settle, 3.4/11.3), glitch-free clock/OCC (2.3/11.2), and the ICG clocking — the timing-critical controls.
• What the RTL/DV engineer sees: the test-mode control logic (ICG test-enable, reset gate, isolation mux) their block must include — mission behavior unchanged (4.4).
• What management cares about: that a power-gated block is fully testable (scan/at-speed) and keeps its power savings — organized control, not a coverage/power trade.

4. Concept — the block across the modes

The block: a clock-gated block (ICG for power, 4.4), with flops, a non-scan/analog interface, and a reset.

Functional (mission) mode:

• test-mode = 0. The ICG gates the clock on its functional enable (power). Reset works normally. Interfaces normal. Test logic transparent.

Scan-shift mode:

• test-mode = 1, scan_enable = 1. The ICG test-enable forces the clock on (4.4) so scan shifts through the block's flops; slow shift clock. Reset gated off (4.4). Interfaces isolated (11.4).

Capture mode:

• test-mode = 1, scan_enable = 0 (settled at every flop before capture, 3.4/11.3). At-speed capture via OCC (2.3) — the ICG passes the OCC-controlled clock. Reset still gated; interfaces isolated.

The controls (all from the mode decoder, 11.2):

• test-mode, scan_enable (dynamic, 3.4), ICG test-enable (force clock on in test, 4.4), OCC control (at-speed, 2.3), reset_gate (gate reset off, 4.4), isolation (drive interfaces known, 11.4).
• Generated coherently, mutually exclusive (11.1), with glitch-free clock selection (11.2).

The result:

• The block steers cleanly functional → scan-shift ↔ capture, testable (clock forced on in scan), valid at-speed (SE settled, OCC, no glitch), reset-safe (gated), and X-clean (isolated) — the whole chapter on one block.

5. Mental Model — one instrument, several playing modes

The clock-gated block under multi-mode control is like a single instrument a musician plays in several modes, with a control panel setting everything at once.

• Functional is performance mode — the instrument plays its music, and its power-saving damper (the clock gate) engages normally.
• Scan-shift is stringing/tuning mode — you override the damper (ICG test-enable forces the clock on) so you can thread new strings (shift patterns) at a slow, careful pace (shift clock).
• Capture is the single test note at full tempo — you let go of the tuning override cleanly (scan-enable settles) and play one note at performance speed (OCC at-speed capture).
• The safety catch (reset) is disengaged during setup so it can't snap the strings (gated off), and noisy neighbors (the analog interface) are muted so they don't bleed into the recording (isolation).
• A single control panel (the mode decoder) sets all of this at once, with firm detents (mutually exclusive modes) and no clicks when switching (glitch-free) — so you never end up half-tuning during a performance.

One instrument, one control panel setting damper-override, tempo, safety-catch, and muting together — that's coherent multi-mode test control of a clock-gated block.

6. Working Example — the control logic and mode table

The test-mode control logic (concise, tri-HDL) and the mode table:

// SystemVerilog - a clock-gated block's test-mode controls (STRUCTURE; representative). Mission unchanged at test_mode=0.
module cg_block_test_ctrl (
  input  logic clk, arst_n, func_enable,      // functional clock, async reset, functional clock-gate enable
  input  logic test_mode, scan_enable,        // from the mode decoder (11.2)
  input  logic occ_clk,                       // at-speed capture clock from OCC (2.3)
  input  logic if_in,                         // non-scan/analog-facing input to isolate (11.4)
  output logic gclk,                          // gated clock to the block's flops
  output logic rst_eff,                       // effective reset (gated in test)
  output logic if_iso                         // isolated interface value in test
);
  // ICG test-enable: force the clock ON in test so scan can shift/capture (4.4)
  logic gate_en = func_enable | test_mode;    // test_mode forces the gate open (ICG cell would latch this)
  // select the clock source: functional gate (mission) vs OCC at-speed (capture) -- GLITCH-FREE mux downstream (11.2)
  logic src_clk = (test_mode & ~scan_enable) ? occ_clk : clk;   // capture uses OCC; else the functional/shift clock
  assign gclk    = src_clk & gate_en;                            // gated clock (test forces it on)
  assign rst_eff = arst_n | test_mode;                           // reset GATED OFF in test (4.4)
  assign if_iso  = test_mode ? 1'b0 : if_in;                     // ISOLATE: drive interface to a known value in test (11.4)
endmodule

// Verilog-2001 - same controls
module cg_block_test_ctrl (clk, arst_n, func_enable, test_mode, scan_enable, occ_clk, if_in, gclk, rst_eff, if_iso);
  input clk, arst_n, func_enable, test_mode, scan_enable, occ_clk, if_in;
  output gclk, rst_eff, if_iso;
  wire gate_en = func_enable | test_mode;                        // ICG test-enable (4.4)
  wire src_clk = (test_mode & ~scan_enable) ? occ_clk : clk;     // OCC at-speed for capture (2.3)
  assign gclk    = src_clk & gate_en;
  assign rst_eff = arst_n | test_mode;                           // reset gated off in test (4.4)
  assign if_iso  = test_mode ? 1'b0 : if_in;                     // isolation (11.4)
endmodule

-- VHDL - same controls
library ieee; use ieee.std_logic_1164.all;
entity cg_block_test_ctrl is
  port (clk, arst_n, func_enable, test_mode, scan_enable, occ_clk, if_in : in std_logic;
        gclk, rst_eff, if_iso : out std_logic);
end entity;
architecture rtl of cg_block_test_ctrl is signal gate_en, src_clk : std_logic; begin
  gate_en <= func_enable or test_mode;                                        -- ICG test-enable (4.4)
  src_clk <= occ_clk when (test_mode = '1' and scan_enable = '0') else clk;   -- OCC at-speed for capture (2.3)
  gclk    <= src_clk and gate_en;
  rst_eff <= arst_n or test_mode;                                             -- reset gated off in test (4.4)
  if_iso  <= '0' when test_mode = '1' else if_in;                             -- isolation (11.4)
end architecture;

# The block's mode-control table - REPRESENTATIVE, SIMPLIFIED, tool-neutral:
  MODE          test_mode  scan_enable  CLOCK to flops           RESET       INTERFACE
  FUNCTIONAL     0          x            gated on func_enable     functional  functional   (power saving; mission)
  SCAN-SHIFT     1          1            forced ON, SHIFT clock   gated off   ISOLATED     (scan can shift, 4.4)
  CAPTURE        1          0 (settled)  forced ON, OCC at-speed  gated off   ISOLATED     (at-speed, 2.3/3.4)
# All controls from the MODE DECODER (11.2), mutually exclusive (11.1), glitch-free clock selection (11.2).
# Note: a real ICG cell latches its enable (glitch-free); the '&'/'or' here is behavioral for clarity.

The waveform shows the block stepping through the modes:

7. Industry Flow — one decoder steers the block

The mode decoder steers the clock-gated block cleanly through all modes:

8. Debugging Session — the clock-gated block gets low coverage

9. Common Mistakes

• No ICG test-enable. The block's clock stays gated off in scan → unclockable/untestable — force it on in test (4.4).
• Chasing coverage with test points. A gated clock can't be fixed by test points — it needs a clock (ICG test-enable).
• Unsettled scan-enable at at-speed capture. Balance/pipeline SE so it settles (3.4/11.3).
• Ungated reset in test. Gate the async reset off (4.4) so it can't corrupt loaded state.
• Un-isolated interfaces. Drive non-scan/analog interfaces known in test (11.4) — no X into the compactor.

10. Industry Best Practices

• Give clock-gated blocks an ICG test-enable (from the mode decoder) — force the clock on in test (4.4).
• Route all test controls from one mode decoder (11.2) — coherent, mutually exclusive, glitch-free.
• Settle scan-enable before capture (3.4/11.3); deliver at-speed via OCC (2.3).
• Gate reset off in test (4.4); isolate non-scan/analog interfaces (11.4).
• Verify the block across all modes (functional/scan-shift/capture) — mission behavior unchanged.

11. Senior Engineer Thinking

• Beginner: "The clock-gated block has low coverage — its logic is hard to test, add test points."
• Senior: "Is the clock reaching the flops in scan? An ICG without a test-enable stays gated off, so the flops can't shift or capture — untestable, and test points can't make a clock. I add the ICG test-enable (from the mode decoder) to force the clock on in test (4.4). Then, with SE settling (3.4), OCC at-speed (2.3), reset gated (4.4), and interfaces isolated (11.4), the block tests cleanly across modes."

The senior fixes a clock-gated block's coverage with the ICG test-enable (clock-controllability), organized by the mode decoder — not test points.

12. Silicon Impact

This capstone assembles every control from Chapter 11 (and 2.3/3.4/4.4) on one realistic block, showing that multi-mode test control is a system, not a set of independent patches. The block — a power-gated one — needs all of it working together: an ICG test-enable to force the clock on in scan/test (4.4) so its flops can be shifted and captured (without it, the block is unclockable and untestable, and test points can't help — a clock-controllability, not hard-logic, problem, as the debugging session shows); a scan-enable that settles before an at-speed capture (3.4/11.3); on-chip clock control delivering that at-speed capture (2.3); a reset gated off yet controllable (4.4); and non-scan/analog interfaces isolated to known values (11.4). The organizing principle is the one the whole chapter built: all these controls come coherently from a top-level mode decoder (11.2), mutually exclusive (one mode at a time, 11.1), with glitch-free clock selection — so the block steers cleanly through functional → scan-shift ↔ capture, keeping its power savings in mission mode while being fully testable in test. The lesson for the RTL/DV engineer is concrete: a clock-gated block must include its test-control logic (ICG test-enable, reset gate, isolation mux), with mission behavior unchanged at test_mode=0 — a deliverable, not an afterthought. And the failure the story catches is the classic one: ad-hoc patches (a test point here, a fix there) that never quite work, versus organized mode control that makes the block testable, at-speed-valid, reset-safe, and X-clean all at once. This closes Chapter 11's test-mode organization arc — the modes (11.1), their muxing (11.2), the big-three signals (11.3), and isolation (11.4) — on a single block, and it sets up Chapter 12 (DFT Constraints & Timing), which must constrain and time these modes in STA (SE-settle, glitch-free/OCC clocking, reset windows, and the mode-specific timing) so that what's logically organized here is also timing-closed in silicon.

13. Engineering Checklist

• ICG test-enable (from the mode decoder) forces the clock on in scan/test (4.4) — block is clockable.
• scan-enable settles before an at-speed capture via OCC (3.4/11.3/2.3).
• Reset gated off in test yet controllable (4.4).
• Non-scan/analog interfaces isolated to known values (11.4) — no X-injection.
• All controls from one mode decoder (11.2), mutually exclusive (11.1), glitch-free clocking; mission unchanged.

14. Try Yourself

1. Write the block's mode-control table (functional/scan-shift/capture → clock/reset/interface).
2. Add the ICG test-enable (force clock on in test) and show the block can now shift in scan.
3. Show scan-enable settling before an OCC at-speed capture (3.4/2.3).
4. Add the reset gate (4.4) and isolation (11.4); confirm reset-safe and X-clean.
5. Confirm all controls come from one mode decoder (11.2), mutually exclusive (11.1), glitch-free.

The control logic is tool-neutral; ICG/OCC are standard cells. A free simulator can model the modes. No paid tool required.

15. Interview Perspective

• Weak: "You test a clock-gated block by turning the clock on in test."
• Good: "The ICG needs a test-enable to force the clock on for scan, plus scan-enable, OCC, reset gating, and isolation."
• Senior: "Testing a clock-gated block needs the whole multi-mode control organization on one block. The ICG must have a test-enable (from the mode decoder) that forces the clock on in scan/test (4.4) — else the flops can't be clocked to shift/capture and are untestable, and test points can't make a clock. scan-enable must settle before an at-speed capture delivered by OCC (3.4/2.3); the async reset must be gated off yet controllable (4.4); and non-scan/analog interfaces must be isolated to known values (11.4). All of it comes coherently from a top-level mode decoder (11.2), mutually exclusive (11.1), with glitch-free clock selection. So the block steers cleanly functional → scan-shift ↔ capture — power-saving in mission, fully testable in test. A clock-gated block's low coverage is a clock-controllability (ICG test-enable) problem, not hard logic."

16. Interview / Review Questions

17. Key Takeaways

• Testing a clock-gated block requires the full multi-mode control organization on one block — the whole chapter (and 2.3/3.4/4.4) working together, generated by a mode decoder.
• The ICG must have a test-enable (from the mode decoder) that forces the clock on in scan/test (4.4) so the block's flops can be shifted and captured — without it the block is unclockable and untestable, and test points can't help (a clock-controllability problem, not hard logic).
• scan-enable must settle before an at-speed capture delivered by OCC (3.4/11.3/2.3); the async reset must be gated off yet controllable (4.4); and non-scan/analog interfaces must be isolated to known values (11.4) — no X-injection.
• All these controls come coherently from a top-level mode decoder (11.2), mutually exclusive (one mode at a time, 11.1), with glitch-free clock selection — so the block steers cleanly through functional → scan-shift ↔ capture, power-saving in mission and fully testable in test (mission behavior unchanged).
• This closes Chapter 11's test-mode organization (modes 11.1, muxing 11.2, big-three 11.3, isolation 11.4) on one block, and sets up Chapter 12 (DFT Constraints & Timing) — constraining and timing these modes in STA (SE-settle, glitch-free/OCC clocking, reset windows). Next: Chapter 12 — DFT Constraints & Timing.

18. Quick Revision

Test control of a clock-gated block (Ch11 capstone). The whole chapter (+2.3/3.4/4.4) on ONE block, all controls from the MODE DECODER (11.2), mutually exclusive (11.1), glitch-free clock (11.2): FUNCTIONAL — ICG gates for power. SCAN-SHIFT — ICG TEST-ENABLE forces the clock ON (4.4) so scan shifts, scan_enable=1, shift clock, reset gated (4.4), interfaces isolated (11.4). CAPTURE — scan_enable settled (3.4/11.3), at-speed via OCC (2.3), reset gated. A clock-gated block's LOW coverage = a clock-controllability problem (ICG has no test-enable → clock stays gated off → flops unclockable/untestable → test points can't make a clock) → add the ICG test-enable, not test points. Steers cleanly functional → scan-shift ↔ capture: testable, at-speed-valid, reset-safe, X-clean. Mission unchanged at test_mode=0. → Ch12 constrains/times these modes. Next: Chapter 12 — DFT Constraints & Timing.