174Total chapters
31Modules
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Buses before signals
Why on-chip buses exist, memory-mapped IO, and open-source SoC interconnect come first — so CYC/STB/ACK and address decoding land on a real mental model.
Interview-ready depth
A leveled interview module plus per-chapter interview weighting — the handshake, decoding, arbitration, RMW, and the Wishbone-vs-AXI questions that trip candidates.
Design → verify → debug
Master/slave/interconnect RTL, a UVM agent, and waveform debugging for missing-ACK, wrong-decode, and arbitration bugs — plus RISC-V/LiteX integration.
Wishbone Complete Curriculum
Your Learning Roadmap
174 chapters · 31 modules — the open on-chip bus — CYC/STB/ACK handshake, decoding, and arbitration.
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Module 1
Why Wishbone Exists
1.1CPU to Peripheral CommunicationPlanned1.2Memory-Mapped IOPlanned1.3Need for Standardized InterconnectsPlanned1.4The Open Hardware MovementPlanned1.5FPGA Design ChallengesPlanned1.6OpenCores OriginsPlanned1.7Why Wishbone Was CreatedPlanned
Module 2
On-Chip Bus Fundamentals
2.1Masters and SlavesPlanned2.2Address SpacePlanned2.3Data TransferPlanned2.4Control SignalsPlanned2.5Bus TransactionsPlanned2.6Shared ResourcesPlanned2.7SoC CommunicationPlanned
Module 3
Wishbone Architecture Overview
3.1Wishbone Architecture OverviewPlanned3.2The Wishbone Mental ModelPlanned3.3The Master InterfacePlanned3.4The Slave InterfacePlanned3.5The InterconnectPlanned3.6Data FlowPlanned3.7Transaction LifecyclePlanned
Module 4
Wishbone Signals Deep Dive
4.1CLK_IPlanned4.2RST_IPlanned4.3ADR_OPlanned4.4DAT_OPlanned4.5DAT_IPlanned4.6WE_OPlanned4.7SEL_OPlanned4.8STB_OPlanned4.9CYC_OPlanned4.10ACK_IPlanned4.11ERR_IPlanned4.12RTY_IPlanned
Module 5
Basic Wishbone Handshake
5.1The Wishbone HandshakePlanned5.2CYC — CyclePlanned5.3STB — StrobePlanned5.4ACK — AcknowledgePlanned5.5Transaction InitiationPlanned5.6Transaction CompletionPlanned5.7Timing RelationshipsPlanned5.8Handshake RulesPlanned
Module 6
Read Transactions
6.1Read Cycle FlowPlanned6.2Address PhasePlanned6.3Data ReturnPlanned6.4ACK GenerationPlanned6.5Wait StatesPlanned6.6Waveform AnalysisPlanned
Module 7
Write Transactions
7.1Write Cycle FlowPlanned7.2Data TransferPlanned7.3ACK TimingPlanned7.4Wait StatesPlanned7.5Waveform AnalysisPlanned
Module 8
Bus Cycles
8.1Single Read CyclePlanned8.2Single Write CyclePlanned8.3Block Transfer CyclePlanned8.4Read-Modify-Write CyclePlanned8.5Cycle TypesPlanned8.6Performance ConsiderationsPlanned
Module 9
Wait States
9.1Why Wait States ExistPlanned9.2Slave DelaysPlanned9.3ACK DelayPlanned9.4Transaction ExtensionPlanned9.5Common BugsPlanned
Module 10
Error Handling
10.1The ERR SignalPlanned10.2Error ResponsesPlanned10.3Invalid AccessesPlanned10.4Timeout HandlingPlanned10.5Debug StrategiesPlanned
Module 11
Retry Mechanism
11.1The RTY SignalPlanned11.2Retry ConceptsPlanned11.3Temporary Resource UnavailabilityPlanned11.4Transaction RestartPlanned11.5Real ExamplesPlanned
Module 12
Address Decoding
12.1Address DecodingPlanned12.2Address MapsPlanned12.3Decoder LogicPlanned12.4Peripheral SelectionPlanned12.5Memory SelectionPlanned12.6Default SlavePlanned12.7Sparse Address SpacesPlanned
Module 13
Byte Selects
13.1SEL SignalsPlanned13.2Byte EnablesPlanned13.3Partial WritesPlanned13.4AlignmentPlanned13.5Data MaskingPlanned
Module 14
Block Transfers
14.1Sequential TransfersPlanned14.2Throughput ImprovementsPlanned14.3Burst-Like BehaviorPlanned14.4Memory AccessesPlanned
Module 15
Read-Modify-Write Cycles
15.1Atomic OperationsPlanned15.2SynchronizationPlanned15.3Shared ResourcesPlanned15.4Multi-Master SystemsPlanned
Module 16
Multi-Master Systems
16.1Why Multiple Masters ExistPlanned16.2CPU + DMA SystemsPlanned16.3Bus OwnershipPlanned16.4Resource SharingPlanned
Module 17
Arbitration
17.1Fixed PriorityPlanned17.2Round RobinPlanned17.3FairnessPlanned17.4StarvationPlanned17.5Arbitration LogicPlanned
Module 18
Interconnect Design
18.1Shared BusPlanned18.2Crossbar ConceptsPlanned18.3RoutingPlanned18.4ScalabilityPlanned18.5Open-Source SoC ExamplesPlanned
Module 19
Wishbone in RISC-V Systems
19.1RISC-V SoCsPlanned19.2LiteXPlanned19.3Open Hardware SystemsPlanned19.4CPU IntegrationPlanned19.5Peripheral IntegrationPlanned
Module 20
Wishbone vs AXI
20.1Complexity ComparisonPlanned20.2Handshake ComparisonPlanned20.3Performance ComparisonPlanned20.4Learning AdvantagesPlanned20.5Design Trade-offsPlanned
Module 21
Wishbone vs APB
21.1SimplicityPlanned21.2ThroughputPlanned21.3Use CasesPlanned21.4Integration Trade-offsPlanned
Module 22
Performance Analysis
22.1ThroughputPlanned22.2LatencyPlanned22.3Wait-State ImpactPlanned22.4Arbitration CostPlanned22.5Design OptimizationPlanned
Module 23
Wishbone RTL Design
23.1Master DesignPlanned23.2Slave DesignPlanned23.3Register Bank DesignPlanned23.4Memory Controller DesignPlanned23.5Address Decoder RTLPlanned23.6Interconnect RTLPlanned
Module 24
Wishbone Slave Design
24.1Register MapsPlanned24.2Read LogicPlanned24.3Write LogicPlanned24.4ACK GenerationPlanned24.5Error GenerationPlanned
Module 25
Wishbone DMA Design
25.1DMA MasterPlanned25.2Memory TransfersPlanned25.3Peripheral TransfersPlanned25.4Arbitration ImpactPlanned
Module 26
Wishbone Verification
26.1Protocol RulesPlanned26.2AssertionsPlanned26.3MonitorsPlanned26.4ScoreboardsPlanned26.5CoveragePlanned26.6UVM ConceptsPlanned
Module 27
Wishbone Debugging
27.1Missing ACKPlanned27.2Wrong Address DecodePlanned27.3Wait-State BugsPlanned27.4Arbitration FailuresPlanned27.5Data CorruptionPlanned27.6Waveform AnalysisPlanned
Module 28
Interview Mastery
28.1Beginner QuestionsPlanned28.2Intermediate QuestionsPlanned28.3Advanced QuestionsPlanned28.4Senior QuestionsPlanned
Module 29
Real Industry Case Studies
29.1FPGA SoCsPlanned29.2LiteX SystemsPlanned29.3Open Hardware ProjectsPlanned29.4Educational CPUsPlanned29.5Research PlatformsPlanned
Module 30
Wishbone Design Review Checklist
30.1RTL ChecklistPlanned30.2Verification ChecklistPlanned30.3Address Map ChecklistPlanned30.4Integration ChecklistPlanned30.5Debug ChecklistPlanned30.6Interview ChecklistPlanned
Module 31
Wishbone Misconceptions Engineers Have
31.1"Wishbone Is Obsolete"Planned31.2"Wishbone Cannot Scale"Planned31.3"Wishbone Is Only for Hobby Projects"Planned31.4"AXI Always Replaces Wishbone"Planned31.5"ACK Must Assert Immediately"Planned31.6"Wishbone Cannot Support DMA"Planned