Verification-focused labs that exercise the SystemVerilog idioms working DV teams use every day — typing, randomization, queues, and SVA.
Each lab takes one SystemVerilog idiom and forces you to use it under realistic pressure — reproducible bugs, real coverage targets, real waveforms. The point is to internalise when each construct is the right tool, not to recite its syntax.
Reproduce a real X-propagation bug, then port the same RTL to `bit` and observe how the bug disappears — and why that is dangerous.
Model the same register file two ways and benchmark synthesis area + simulation memory footprint.
Refactor a numeric-encoded FSM to a typed `enum` state and prove the waveform names are now self-documenting.
Model an Ethernet-like header as a packed struct and reuse the same definition in RTL, monitor, and scoreboard.
Build a producer/consumer scoreboard that uses queues for ordering and a mailbox for cross-thread hand-off.
Write a randomized stimulus class with three layered constraints (legal, biased, corner) and observe coverage convergence.
Write SVA properties for a simple handshake protocol and prove they catch three pre-seeded RTL bugs.