SystemVerilog Labs.
Build production-grade SystemVerilog reasoning from RTL constructs through assertions, constrained random, coverage and verification architecture. The curriculum runs design first and verification second — types and interfaces before temporal properties, a working self-checking testbench before a single class, and classes before the randomisation that lives inside them.
A progressive path — RTL constructs to verification architecture
SystemVerilog RTL Foundations
The constructs that changed how RTL is written — logic, the always_* family, and what each one tells a synthesiser.
Strong Typing & Data Modeling
Enums, structs, unions and the dynamic array family — describing hardware and transactions with types that catch mistakes.
Parameters, Packages & Reuse
Parameterised, packaged, generated RTL — the difference between a module you wrote once and a module a team can reuse.
Interfaces & Modports
Bundling a bus, giving each side a view of it, and sampling it without a race — the DUT/testbench boundary done properly.
Assertions & Temporal Reasoning
Saying what must be true across time: sequences, properties, implication, repetition, and the sampled-value functions.
Testbench Architecture
Stimulus, checking and a scoreboard, built procedurally — a self-checking regression before a single class appears.
OOP Verification Foundations
Classes, inheritance and polymorphism applied to the testbench you already built — transactions and reusable components.
Concurrency & Communication
fork/join, process control, events, mailboxes and semaphores — making concurrent components talk deterministically.
Constrained Random
Generating legal, interesting, reproducible stimulus — constraints, distributions, solve ordering, and debugging failures.
Functional Coverage
Measuring what the random stimulus actually reached — covergroups, bins, crosses, and closing a real coverage hole.
Integrated Verification Projects
Four complete environments: interface, assertions, class-based components, randomisation and coverage against a real DUT.
All 60 labs & projects
Search and filter the full curriculum. Titles, previews and metadata are free to browse — full lab content requires the labs package.
- Lab 1SystemVerilog RTL Foundations
The logic Type & Four-State Debugging
Replace wire/reg with logic, then deliberately drive a net from two places and read the resulting X in the waveform to learn what four-state simulation is actually telling you.
Beginner·30 min·Testbench·1 challengeBeginnerPublishedPaid - Lab 2SystemVerilog RTL Foundations
always_comb, always_ff and always_latch
Write the same block three ways and compare what each one asks the tool for — then trigger a real inferred-latch warning and fix it by making the intent explicit.
Beginner·35 min·Testbench·1 challengeBeginnerPublishedPaid - Lab 3SystemVerilog RTL Foundations
Packed vs Unpacked Arrays
Model a register file two ways and discover which dimension you can slice, which you can assign as a whole, and which one a synthesiser turns into memory.
Beginner·35 min·Testbench·1 challengeBeginnerPublishedPaid - Lab 4SystemVerilog RTL Foundations
Part-Selects, Concatenation & Streaming Operators
Pack and unpack a header field by field, then do it in one line with a streaming operator, and verify both produce bit-identical results on every alignment.
Beginner·35 min·Testbench·1 challengeBeginnerComing soonPaid - Lab 5SystemVerilog RTL Foundations
unique, priority and the Cost of a Careless case
Build a decoder with overlapping case items, then use unique and priority to state which overlaps are legal — and watch a simulation-time violation catch a bug synthesis silently accepted.
Intermediate·40 min·Testbench·2 challengesIntermediateComing soonPaid - Lab 6SystemVerilog RTL Foundations
Width, Casting & Signedness
Track a value through an expression that silently truncates it, then fix the width with a static cast and prove the corrected arithmetic against a signed reference model.
Intermediate·40 min·Testbench·2 challengesIntermediateComing soonPaid - Lab 7Strong Typing & Data Modeling
Enumerated Types for State Machines
Rebuild a one-hot FSM with an enum, get readable state names in the waveform for free, and use enum methods to walk and bound the legal state set.
Beginner·40 min·Testbench·1 challengeBeginnerComing soonPaid - Lab 8Strong Typing & Data Modeling
Packed Structs for Bus Fields
Describe a bus header as a packed struct, assign it as one vector on the wire and as named fields in the logic, and prove the two views cannot drift apart.
Intermediate·40 min·Testbench·1 challengeIntermediateComing soonPaid - Lab 9Strong Typing & Data Modeling
Unpacked Structs & Unions
Model a descriptor whose payload is interpreted two different ways, then use a packed union to overlay both views and test that writing one really does change the other.
Intermediate·40 min·Testbench·1 challengeIntermediateComing soonPaid - Lab 10Strong Typing & Data Modeling
Queues for Variable-Depth Transaction Storage
Model variable-depth transaction storage with a queue, then verify push/pop ordering, boundary behaviour at empty and full, and what happens when you delete from the middle.
Intermediate·45 min·Testbench·2 challengesIntermediateComing soonPaid - Lab 11Strong Typing & Data Modeling
Dynamic & Associative Arrays
Size a buffer at run time with a dynamic array, then model a sparse memory with an associative array and check that reading an unwritten key is handled rather than assumed.
Intermediate·45 min·Testbench·2 challengesIntermediateComing soonPaid - Lab 12Strong Typing & Data Modeling
Array Manipulation & Reduction Methods
Replace hand-written search loops with sum, find_first, unique and sort, then use them to build a compact scoreboard query that stays readable as the data grows.
Intermediate·40 min·Testbench·2 challengesIntermediateComing soonPaid - Lab 13Parameters, Packages & Reuse
Parameters, localparams & Derived Widths
Take a fixed-width design parametric, derive every dependent width instead of restating it, and prove three configurations pass the same testbench unchanged.
Beginner·40 min·Testbench·1 challengeBeginnerComing soonPaid - Lab 14Parameters, Packages & Reuse
Packages, Scope & Import Discipline
Move shared types and constants into a package, then compare wildcard import against explicit import by deliberately creating a name collision and resolving it.
Intermediate·40 min·Testbench·1 challengeIntermediateComing soonPaid - Lab 15Parameters, Packages & Reuse
Functions, Tasks & Automatic Lifetime
Call the same task from two concurrent threads, watch static storage corrupt both, then fix it with automatic lifetime and understand why testbench code defaults differently.
Intermediate·45 min·Testbench·2 challengesIntermediateComing soonPaid - Lab 16Parameters, Packages & Reuse
Type Parameters & Generic Modules
Parameterise a module by TYPE rather than by width, so one synchroniser or one register slice serves a struct, an enum and a plain vector without edits.
Advanced·50 min·Testbench·2 challengesAdvancedComing soonPaid - Lab 17Parameters, Packages & Reuse
Generate Blocks & Structural Replication
Build an N-stage pipeline and a tree reduction with generate, then use the generated hierarchy names to reach into any stage from the testbench.
Advanced·50 min·Testbench·2 challengesAdvancedComing soonPaid - Lab 18Interfaces & Modports
Interfaces for Bus Bundling
Collapse a fifteen-signal port list into one interface, connect a DUT and a testbench through it, and add a signal without touching a single port declaration.
Intermediate·45 min·Testbench·1 challengeIntermediateComing soonPaid - Lab 19Interfaces & Modports
Modports & Direction Contracts
Give each side of an interface its own view with modports, then attempt to drive a signal the DUT should only read and let the compiler enforce the contract for you.
Intermediate·40 min·Testbench·1 challengeIntermediateComing soonPaid - Lab 20Interfaces & Modports
Clocking Blocks & Sampling Skew
Reproduce a real testbench race where a driver and a monitor disagree about a value at the clock edge, then eliminate it with a clocking block and explain the skew that fixed it.
Advanced·55 min·Testbench·2 challengesAdvancedComing soonPaid - Lab 21Interfaces & Modports
Virtual Interfaces & the Static/Dynamic Boundary
Pass a physical interface into code that is not part of the module hierarchy, and understand why a handle — not the interface itself — is what crosses that boundary.
Advanced·55 min·Testbench·2 challengesAdvancedComing soonPaid - Lab 22Interfaces & Modports
Designing the DUT/Testbench Boundary
Assemble an interface, its modports and its clocking block into one reusable bus agent connection, then reconnect a second DUT to it with no testbench changes.
Advanced·60 min·Testbench·2 challengesAdvancedComing soonPaid - Lab 23Assertions & Temporal Reasoning
Immediate Assertions & Executable Specification
Turn three sentences from a spec into immediate assertions inside the design, then break the design three ways and read the severity, the message and the source line each one reports.
Beginner·40 min·Testbench·1 challengeBeginnerComing soonPaid - Lab 24Assertions & Temporal Reasoning
Concurrent Assertions & the Sampling Model
Write your first property with a clocking event and discover why it reads the value from before the edge — the preponed region is the whole reason assertions are stable.
Intermediate·50 min·Testbench·2 challengesIntermediateComing soonPaid - Lab 25Assertions & Temporal Reasoning
Sequences & Implication Operators
Express a request/grant contract with a sequence, then compare overlapping against non-overlapping implication on the same waveform and see exactly which cycle each one checks.
Intermediate·55 min·Testbench·2 challengesIntermediateComing soonPaid - Lab 26Assertions & Temporal Reasoning
Repetition, Delay Ranges & Unbounded Windows
Specify a response that must arrive between two and eight cycles, then use consecutive, non-consecutive and goto repetition to describe a burst whose length is not fixed.
Advanced·60 min·Testbench·3 challengesAdvancedComing soonPaid - Lab 27Assertions & Temporal Reasoning
$rose, $fell, $stable and $past
Check an edge-triggered protocol using sampled-value functions, then use $past with a delay to assert that an output equals a function of an input several cycles earlier.
Advanced·55 min·Testbench·2 challengesAdvancedComing soonPaid - Lab 28Assertions & Temporal Reasoning
disable iff & Assertions Under Reset
Watch every property in a design fire spuriously during reset, then scope them correctly with disable iff and reason about which checks should genuinely survive a reset.
Advanced·50 min·Testbench·2 challengesAdvancedComing soonPaid - Lab 29Assertions & Temporal Reasoning
assert, assume and cover — Three Different Claims
Take one property and use it three ways: as an obligation on the design, as a constraint on its inputs, and as evidence that a scenario was actually exercised.
Advanced·55 min·Testbench·2 challengesAdvancedComing soonPaid - Lab 30Testbench Architecture
Anatomy of a Self-Checking Testbench
Separate stimulus, checking and reporting into distinct responsibilities, and end with a regression that prints a pass/fail verdict instead of a waveform to inspect by hand.
Intermediate·50 min·Testbench·2 challengesIntermediateComing soonPaid - Lab 31Testbench Architecture
Directed Stimulus & Corner-Case Design
Enumerate the boundary conditions of a design on paper first, then write directed tests for each and measure how many bugs a purely random run would have missed.
Intermediate·50 min·Testbench·2 challengesIntermediateComing soonPaid - Lab 32Testbench Architecture
Timeouts, Bounds & Regressions That Fail Fast
Replace every unbounded wait in a testbench with a bounded one, so a hung design reports a clear failure in finite time instead of stalling the regression overnight.
Intermediate·45 min·Testbench·1 challengeIntermediateComing soonPaid - Lab 33Testbench Architecture
Reference Models & Independent Oracles
Write a checker that computes the expected result a different way from the DUT, and see why an oracle that mirrors the design agrees with its bugs.
Advanced·55 min·Testbench·2 challengesAdvancedComing soonPaid - Lab 34Testbench Architecture
Scoreboards & Ordering Checks
Build a queue-based scoreboard that proves a design neither loses, duplicates nor reorders data — then break the DUT's ordering and confirm the scoreboard localises it.
Advanced·60 min·Testbench·2 challengesAdvancedComing soonPaid - Lab 35OOP Verification Foundations
Classes, Handles & Construction
Refactor the procedural stimulus of the previous module into a class, then assign one handle to another and discover you have two names for one object, not two objects.
Intermediate·50 min·Testbench·2 challengesIntermediateComing soonPaid - Lab 36OOP Verification Foundations
Transaction Classes & the Item Abstraction
Model one bus operation as an object rather than a pile of signals, give it print and compare behaviour, and drive a DUT entirely in terms of transactions.
Intermediate·50 min·Testbench·2 challengesIntermediateComing soonPaid - Lab 37OOP Verification Foundations
Inheritance & Method Overriding
Extend a base transaction into an error-injecting variant, override just the behaviour that differs, and use super to keep the parent's work rather than copying it.
Advanced·55 min·Testbench·2 challengesAdvancedComing soonPaid - Lab 38OOP Verification Foundations
Polymorphism & Virtual Methods
Hold a derived object in a base handle, call a method that exists in both, and use the non-virtual case to see exactly which mistake the virtual keyword prevents.
Advanced·55 min·Testbench·3 challengesAdvancedComing soonPaid - Lab 39OOP Verification Foundations
Abstract Classes & Pure Virtual Contracts
Define a driver contract that cannot be instantiated but must be implemented, so every protocol-specific driver in a testbench is forced to provide the same entry points.
Advanced·55 min·Testbench·2 challengesAdvancedComing soonPaid - Lab 40OOP Verification Foundations
Deep Copy, Compare & Cloning
Shallow-copy a transaction that owns a nested object, watch both copies change together, then implement a proper deep copy and a compare that a scoreboard can trust.
Advanced·55 min·Testbench·2 challengesAdvancedComing soonPaid - Lab 41Concurrency & Communication
fork/join, join_any and join_none
Run a driver and a monitor concurrently three different ways and observe precisely when each variant releases the parent thread — and which one leaves work still running.
Intermediate·50 min·Testbench·2 challengesIntermediateComing soonPaid - Lab 42Concurrency & Communication
Process Control, wait fork & disable fork
Start a timeout thread alongside a transfer, let whichever finishes first win, then kill the loser cleanly — and see what a leaked process does to the next test.
Advanced·55 min·Testbench·2 challengesAdvancedComing soonPaid - Lab 43Concurrency & Communication
Events & Thread Synchronisation
Synchronise two threads with an event, hit the classic race where the trigger is missed because the waiter arrived late, and fix it with a persistent triggered check.
Advanced·50 min·Testbench·2 challengesAdvancedComing soonPaid - Lab 44Concurrency & Communication
Mailboxes for Component Communication
Connect a generator, a driver and a monitor through mailboxes so no component reaches into another, then bound one and watch back-pressure appear on its own.
Advanced·60 min·Testbench·2 challengesAdvancedComing soonPaid - Lab 45Concurrency & Communication
Semaphores & Shared Resource Arbitration
Let two threads drive one bus at once and watch the transactions interleave into nonsense, then serialise access with a semaphore and confirm every transfer completes intact.
Advanced·50 min·Testbench·2 challengesAdvancedComing soonPaid - Lab 46Constrained Random
rand, randc and the randomize() Call
Randomise a transaction, check the return value that most testbenches ignore, and compare rand against randc by counting how long each takes to repeat a value.
Intermediate·45 min·Testbench·2 challengesIntermediateComing soonPaid - Lab 47Constrained Random
Constraint Blocks, inside & Ranges
Restrict an address to a legal window with inside, then add a second constraint that contradicts the first and read the solver failure rather than guessing at it.
Intermediate·50 min·Testbench·2 challengesIntermediateComing soonPaid - Lab 48Constrained Random
dist & Weighted Distributions
Bias a stimulus stream toward its interesting cases with dist, then histogram thousands of runs to confirm the weights produced the profile you intended.
Advanced·50 min·Testbench·2 challengesAdvancedComing soonPaid - Lab 49Constrained Random
Constraint Implication & solve...before
Make one field depend on another with implication, then use solve...before to change the solution distribution without changing which solutions are legal.
Advanced·55 min·Testbench·3 challengesAdvancedComing soonPaid - Lab 50Constrained Random
Array, Size & foreach Constraints
Randomise a burst whose length, addresses and payload must all agree, using size and foreach constraints so no illegal combination can be generated at all.
Advanced·60 min·Testbench·2 challengesAdvancedComing soonPaid - Lab 51Constrained Random
Inline Constraints, pre/post_randomize & Debugging
Narrow one call with an inline constraint, derive a dependent field in post_randomize, and work through an over-constrained failure to a solver you can actually reason about.
Advanced·60 min·Testbench·3 challengesAdvancedComing soonPaid - Lab 52Functional Coverage
Covergroups & Coverpoints
Sample a transaction stream into a covergroup, then compare what the coverage report claims against what the stimulus actually did — and find the gap between them.
Intermediate·50 min·Testbench·2 challengesIntermediateComing soonPaid - Lab 53Functional Coverage
Bins — Automatic, Explicit & Why It Matters
Let the tool auto-bin a wide field, see the meaningless numbers it produces, then define bins that correspond to actual design behaviour instead of value ranges.
Intermediate·50 min·Testbench·2 challengesIntermediateComing soonPaid - Lab 54Functional Coverage
Transition, illegal_bins & ignore_bins
Cover a state machine's legal transitions rather than its states, mark the illegal ones so they fail loudly, and ignore the unreachable ones instead of chasing them forever.
Advanced·55 min·Testbench·2 challengesAdvancedComing soonPaid - Lab 55Functional Coverage
Cross Coverage & Combination Explosion
Cross three coverpoints, watch the bin count explode into thousands, then use binsof and intersect to keep only the combinations that describe real scenarios.
Advanced·60 min·Testbench·3 challengesAdvancedComing soonPaid - Lab 56Functional Coverage
Coverage-Driven Closure
Run a regression to a coverage plateau, read the report to find the hole, write the constraint that reaches it, and prove the number moved for the reason you claimed.
Advanced·70 min·Testbench·3 challengesAdvancedComing soonPaid - ProjectPortfolio Project
Project — Synchronous FIFO Verification Environment
Verify a parameterised FIFO end to end: an interface with a clocking block, assertions for the full/empty contract, a class-based environment, randomised traffic and a coverage model that proves both boundaries were hit.
Advanced·150 min·Testbench·3 challengesAdvancedComing soonPaid - ProjectPortfolio Project
Project — Round-Robin Arbiter Verification Environment
Prove fairness and starvation-freedom on a multi-requester arbiter using temporal properties for the grant contract, constrained random request patterns, and cross coverage over requester combinations.
Advanced·150 min·Testbench·3 challengesAdvancedComing soonPaid - ProjectPortfolio Project
Project — APB-Style Peripheral Verification
Build a reusable bus agent for a simple register-mapped peripheral: modport-enforced connections, protocol assertions for the setup/access phases, a register scoreboard and a coverage model over the address map.
Advanced·180 min·Testbench·4 challengesAdvancedComing soonPaid - ProjectPortfolio Project
Project — UART Verification Environment
Verify a serial link where the testbench must recover timing rather than share it: sampling-accurate monitors, framing and false-start assertions, randomised baud error, and coverage over frame content and error conditions.
Advanced·180 min·Testbench·4 challengesAdvancedComing soonPaid