Module 1
Why sed Matters in VLSI
1.1Why sed ExistsPlanned1.2sed in Semiconductor WorkflowsPlanned1.3sed vs grepPlanned1.4sed vs awkPlanned1.5sed vs PythonPlanned
2.1Stream Editing ConceptPlanned2.2Pattern SpacePlanned2.3Input → Transformation → OutputPlanned
Module 3
Basic Substitution
3.1Search and ReplacePlanned3.2Global ReplacementPlanned3.3Targeted ReplacementPlanned
Module 4
Working with RTL Filelists
4.1Update Include PathsPlanned4.2Replace Directory StructuresPlanned4.3Normalize FilelistsPlanned
Module 5
Working with Simulation Scripts
5.1VCS ScriptsPlanned5.2Xcelium ScriptsPlanned5.3Questa ScriptsPlanned
6.1Delete LinesPlanned6.2Print LinesPlanned6.3Range OperationsPlanned
Module 7
Regex for VLSI Engineers
7.1Pattern MatchingPlanned7.2Character ClassesPlanned7.3GroupsPlanned7.4AnchorsPlanned
Module 8
In-Place File Editing
8.1-i OptionPlanned8.2Safe EditingPlanned8.3Backup FilesPlanned
Module 9
Configuration Management
9.1Simulation ConfigsPlanned9.2Tool ConfigsPlanned9.3Environment ConfigsPlanned
Module 10
Synthesis Flow Maintenance
10.1Library PathsPlanned10.2Constraint ReferencesPlanned10.3Run DirectoriesPlanned
Module 11
STA Flow Maintenance
11.1SDC ReferencesPlanned11.2Report DirectoriesPlanned11.3Timing CornersPlanned
12.1Remove NoisePlanned12.2Normalize OutputPlanned12.3Filter ReportsPlanned
13.1Extract Useful InformationPlanned13.2Remove BoilerplatePlanned13.3Normalize LogsPlanned
14.1PipelinesPlanned14.2Automation ScriptsPlanned
15.1When to Use sedPlanned15.2When to Use awkPlanned15.3Hybrid Parsing FlowsPlanned
Module 16
sed with Tcl and Python
16.1Tcl Generates ScriptsPlanned16.2sed Updates PathsPlanned16.3Python Analyzes OutputsPlanned
Module 17
Mass RTL Refactoring
17.1Rename SignalsPlanned17.2Rename ModulesPlanned17.3Update IncludesPlanned17.4Update DefinesPlanned
Module 18
Debugging sed Commands
18.1Common ErrorsPlanned18.2Regex ProblemsPlanned18.3Unexpected ReplacementsPlanned18.4Safe Testing TechniquesPlanned
Module 19
Industry Case Studies
19.1Filelist MigrationPlanned19.2RTL Path MigrationPlanned19.3Simulation Script UpgradePlanned19.4Constraint File UpdatesPlanned19.5Regression CleanupPlanned
Module 20
sed Interview Mastery for VLSI
20.1BeginnerPlanned20.2IntermediatePlanned20.3AdvancedPlanned
Module 21
sed Design Review Checklist
21.1Safety ChecklistPlanned21.2Regex ChecklistPlanned21.3Filelist ChecklistPlanned21.4Migration ChecklistPlanned21.5Automation ChecklistPlanned
Module 22
sed Misconceptions VLSI Engineers Have
22.1sed Is ObsoletePlanned22.2grep Can Replace sedPlanned22.3Python Always Replaces sedPlanned22.4sed Is Only for Linux AdminsPlanned22.5Search/Replace Can Be Done ManuallyPlanned