Module 1
Why Perl Still Matters in VLSI
1.1Perl's Historical Role in EDAPlanned1.2Why Legacy Flows Still Use PerlPlanned1.3Perl vs PythonPlanned1.4When Engineers Encounter Perl TodayPlanned
Module 2
Perl Fundamentals
2.1ScalarsPlanned2.2ArraysPlanned2.3HashesPlanned2.4OperatorsPlanned2.5Input/OutputPlanned
3.1if / elsif / elsePlanned3.2for and foreachPlanned3.3whilePlanned3.4last and nextPlanned
4.1Defining SubroutinesPlanned4.2Argument HandlingPlanned4.3Return ValuesPlanned4.4Reusable EDA HelpersPlanned
5.1Reading FilesPlanned5.2Writing FilesPlanned5.3Directory ProcessingPlanned5.4File TestsPlanned
Module 6
Regular Expressions
6.1Pattern MatchingPlanned6.2Capture GroupsPlanned6.3SubstitutionsPlanned6.4Advanced RegexPlanned6.5Multiline and /s /m ModesPlanned
7.1Simulation Log CleanupPlanned7.2Configuration ProcessingPlanned7.3Coverage Log ProcessingPlanned7.4Timing Report CleanupPlanned
Module 8
Hashes for EDA Data
8.1Hashes as Test ResultsPlanned8.2Hashes as Coverage DataPlanned8.3Hashes as Timing MetricsPlanned8.4Hashes of HashesPlanned8.5Report Summaries from HashesPlanned
Module 9
Filelist Generation
9.1Finding RTL SourcesPlanned9.2Removing DuplicatesPlanned9.3Generating Include ListsPlanned
Module 10
Netlist Processing
10.1Reading NetlistsPlanned10.2Analyzing NetlistsPlanned10.3Extracting HierarchyPlanned10.4Extracting InstancesPlanned
Module 11
Synthesis Report Parsing
11.1Area ReportsPlanned11.2Cell CountsPlanned11.3Hierarchy ReportsPlanned
Module 12
STA Report Parsing
12.1Slack ExtractionPlanned12.2Violation DetectionPlanned12.3Clock AnalysisPlanned12.4PrimeTime ReportsPlanned12.5Tempus ReportsPlanned
Module 13
Regression Automation
13.1Test ListsPlanned13.2Result AggregationPlanned13.3Failure DetectionPlanned
Module 14
UVM Log Analysis
14.1Extracting UVM_INFOPlanned14.2Extracting UVM_WARNINGPlanned14.3Extracting UVM_ERRORPlanned14.4Extracting UVM_FATALPlanned14.5Generating UVM SummariesPlanned
Module 15
CSV and Report Generation
15.1CSV GenerationPlanned15.2Text SummariesPlanned15.3Regression ReportsPlanned15.4Coverage SummariesPlanned
16.1Bash Launches PerlPlanned16.2Perl Generates ReportsPlanned
17.1Tcl Runs ToolsPlanned17.2Perl Parses ReportsPlanned
Module 18
Perl to Python Migration
18.1Understanding Legacy ScriptsPlanned18.2Migration StrategiesPlanned18.3Incremental ConversionPlanned18.4Common PitfallsPlanned18.5Side-by-Side ValidationPlanned
19.1WarningsPlanned19.2Strict ModePlanned19.3Regex DebuggingPlanned19.4File Handling ErrorsPlanned19.5Maintainability PracticesPlanned
Module 20
Industry Case Studies
20.1Netlist AnalyzerPlanned20.2Timing Report ParserPlanned20.3Coverage Report ParserPlanned20.4Regression Dashboard GeneratorPlanned20.5Legacy Flow MaintenancePlanned
Module 21
Perl Interview Mastery for VLSI
21.1BeginnerPlanned21.2IntermediatePlanned21.3AdvancedPlanned
Module 22
Perl Design Review Checklist
22.1Regex ChecklistPlanned22.2Parsing ChecklistPlanned22.3Maintainability ChecklistPlanned22.4Migration ChecklistPlanned22.5Automation ChecklistPlanned
Module 23
Perl Misconceptions VLSI Engineers Have
23.1Perl Is Completely DeadPlanned23.2Python Replaced All Perl CodePlanned23.3Legacy Scripts Should Be Rewritten ImmediatelyPlanned23.4Regex-Heavy Automation Is Impossible Without PerlPlanned23.5Learning Perl Has No Career ValuePlanned