175Total chapters
28Modules
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0 / 28Active modules
Electrical first principles
Why two wires, why open-drain, why pull-ups — the physics is taught before START/STOP, so the protocol mechanics finally make sense.
Interview-ready depth
A leveled interview module plus per-chapter interview weighting — open-drain, arbitration, clock stretching, and the misconceptions that trip candidates.
Design → verify → debug
Master/slave FSM RTL, open-drain modeling, SVA + a UVM agent, and waveform-based debugging for stuck buses and missing ACKs — the full loop.
I²C Complete Curriculum
Your Learning Roadmap
175 chapters · 28 modules — open-drain electricals, arbitration, clock stretching, and silicon-grade RTL.
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Module 1
Why I²C Exists
1.1Communication Between ChipsPlanned1.2The PCB Wiring ProblemPlanned1.3Parallel Bus LimitationsPlanned1.4Serial Communication BasicsPlanned1.5Why Philips Created I²CPlanned1.6Typical I²C SystemsPlanned1.7Sensors, EEPROMs & PMICsPlanned1.8I²C vs SPI OverviewPlanned
Module 2
I²C Physical Layer Fundamentals
2.1The SDA SignalPlanned2.2The SCL SignalPlanned2.3The Open-Drain ConceptPlanned2.4Open-Collector HistoryPlanned2.5Pull-Up ResistorsPlanned2.6Wired-AND BehaviorPlanned2.7Bus Idle StatePlanned2.8Bus Electrical CharacteristicsPlanned
Module 3
Understanding Open-Drain Design
3.1Why Push-Pull FailsPlanned3.2Bus ContentionPlanned3.3Multiple DriversPlanned3.4Wired LogicPlanned3.5Open-Drain WaveformsPlanned3.6Real Hardware ExamplesPlanned3.7RTL Modeling of Open DrainPlanned
Module 4
I²C Bus Architecture
4.1Master DevicesPlanned4.2Slave DevicesPlanned4.3Multi-Slave SystemsPlanned4.4Multi-Master SystemsPlanned4.5The Shared Bus ConceptPlanned4.6Device ConnectionsPlanned4.7Typical SoC ExamplesPlanned
Module 5
I²C Signal Timing
5.1Clock GenerationPlanned5.2Data Valid WindowsPlanned5.3Setup TimePlanned5.4Hold TimePlanned5.5Timing ConstraintsPlanned5.6Timing DiagramsPlanned5.7Clock SynchronizationPlanned
Module 6
START and STOP Conditions
6.1Bus IdlePlanned6.2The START ConditionPlanned6.3Repeated STARTPlanned6.4The STOP ConditionPlanned6.5Timing RequirementsPlanned6.6Waveform AnalysisPlanned6.7Common ErrorsPlanned
Module 7
I²C Frame Format
7.1Byte StructurePlanned7.2Bit OrderingPlanned7.3MSB FirstPlanned7.4The Address FieldPlanned7.5The R/W BitPlanned7.6The ACK CyclePlanned7.7The NACK CyclePlanned
Module 8
Addressing
8.17-Bit AddressingPlanned8.210-Bit AddressingPlanned8.3Reserved AddressesPlanned8.4The General Call AddressPlanned8.5Address AllocationPlanned8.6Address ConflictsPlanned8.7Address DecodingPlanned
Module 9
Acknowledge Mechanism
9.1ACK FundamentalsPlanned9.2NACK FundamentalsPlanned9.3ACK TimingPlanned9.4Slave ACKPlanned9.5Master ACKPlanned9.6End-of-Transfer NACKPlanned9.7Debug ExamplesPlanned
Module 10
Read Transactions
10.1Basic ReadPlanned10.2Address PhasePlanned10.3Data PhasePlanned10.4Master ReceiverPlanned10.5Slave TransmitterPlanned10.6Read TimingPlanned10.7Read WaveformsPlanned
Module 11
Write Transactions
11.1Basic WritePlanned11.2Address PhasePlanned11.3Data PhasePlanned11.4Master TransmitterPlanned11.5Slave ReceiverPlanned11.6Write TimingPlanned11.7Write WaveformsPlanned
Module 12
Combined Transactions
12.1Write Then ReadPlanned12.2Register AccessPlanned12.3Repeated START in PracticePlanned12.4Sensor Access ExamplesPlanned12.5EEPROM Access ExamplesPlanned
Module 13
Clock Stretching
13.1Why Clock Stretching ExistsPlanned13.2Slave DelaysPlanned13.3Stretching MechanismPlanned13.4Timing ImpactPlanned13.5RTL HandlingPlanned13.6Verification ChallengesPlanned
Module 14
Multi-Master Operation
14.1Why Multiple Masters ExistPlanned14.2Arbitration FundamentalsPlanned14.3Arbitration TimingPlanned14.4Bus OwnershipPlanned14.5Arbitration ExamplesPlanned14.6Corner CasesPlanned
Module 15
Bus Arbitration
15.1Wired-AND ArbitrationPlanned15.2Bit-Level ArbitrationPlanned15.3Losing ArbitrationPlanned15.4Winning ArbitrationPlanned15.5Real ExamplesPlanned15.6Debugging Arbitration FailuresPlanned
Module 16
Clock Synchronization
16.1Multi-Master ClocksPlanned16.2Clock Synchronization RulesPlanned16.3Fast vs Slow MastersPlanned16.4Synchronization ExamplesPlanned
Module 17
I²C Speed Modes
17.1Standard Mode (100 kHz)Planned17.2Fast Mode (400 kHz)Planned17.3Fast Mode Plus (1 MHz)Planned17.4High-Speed Mode (3.4 MHz)Planned17.5Ultra-Fast ModePlanned17.6Design ImplicationsPlanned
Module 18
Special I²C Features
18.1General CallPlanned18.2Software ResetPlanned18.3Device IdentificationPlanned18.4Reserved AddressesPlanned18.5Broadcast ConceptsPlanned
Module 19
EEPROM Communication
19.1EEPROM BasicsPlanned19.2EEPROM AddressingPlanned19.3Sequential ReadsPlanned19.4Page WritesPlanned19.5Acknowledge PollingPlanned19.6Common Industry ExamplesPlanned
Module 20
Sensor Interfaces
20.1Temperature SensorsPlanned20.2AccelerometersPlanned20.3RTC DevicesPlanned20.4PMIC CommunicationPlanned20.5Real Register MapsPlanned
Module 21
I²C RTL Design
21.1Master FSM DesignPlanned21.2Slave FSM DesignPlanned21.3Open-Drain RTLPlanned21.4Clock Generation (RTL)Planned21.5Arbitration LogicPlanned21.6Error HandlingPlanned21.7Synthesis ConsiderationsPlanned
Module 22
I²C Verification
22.1Verification StrategyPlanned22.2Bus Functional ModelsPlanned22.3Protocol CheckersPlanned22.4AssertionsPlanned22.5Functional CoveragePlanned22.6UVM Agent DesignPlanned
Module 23
I²C Debugging
23.1Missing ACKPlanned23.2Address ErrorsPlanned23.3Clock Stretch IssuesPlanned23.4Arbitration FailuresPlanned23.5Stuck BusPlanned23.6Pull-Up ProblemsPlanned23.7Electrical IssuesPlanned
Module 24
I²C Interview Mastery
24.1Beginner QuestionsPlanned24.2Intermediate QuestionsPlanned24.3Advanced QuestionsPlanned24.4Senior QuestionsPlanned
Module 25
I²C vs Other Protocols
25.1I²C vs SPIPlanned25.2I²C vs UARTPlanned25.3I²C vs SMBusPlanned25.4I²C vs PMBusPlanned25.5I²C vs AXI-LitePlanned
Module 26
Real Industry Case Studies
26.1SoC Bring-UpPlanned26.2Sensor NetworksPlanned26.3Power ManagementPlanned26.4FPGA SystemsPlanned26.5Server BoardsPlanned26.6Consumer ElectronicsPlanned
Module 27
I²C Design Review Checklist
27.1RTL ChecklistPlanned27.2Verification ChecklistPlanned27.3Timing ChecklistPlanned27.4Electrical ChecklistPlanned27.5Debug ChecklistPlanned27.6Interview ChecklistPlanned
Module 28
I²C Misconceptions Engineers Have
28.1"Pull-Ups Are Optional"Planned28.2"SDA Can Change Anytime"Planned28.3"Arbitration Happens Per Transaction"Planned28.4"Clock Stretching Is Rare"Planned28.5"I²C Is Always Slower Than SPI"Planned28.6"Open Drain Is Only for Legacy Reasons"Planned