183Total chapters
32Modules
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Networks before frame fields
Why networking exists, shared-media limits, and packet switching come first — so the MAC/PHY split, frames, and switching land on a real mental model.
Interview-ready depth
A leveled interview module plus per-chapter interview weighting — MAC vs PHY, RGMII, VLANs, switching, PTP, DMA, and the misconceptions that trip candidates.
Design → verify → debug
MAC RTL (frame parser, CRC engine, DMA, FIFOs), a UVM Ethernet agent, and packet-capture debugging for CRC errors, link failures, and DMA issues.
Ethernet Complete Curriculum
Your Learning Roadmap
183 chapters · 32 modules — MAC/PHY, frames, switching, VLANs, PTP, TSN — networks down to RTL.
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Module 1
Why Ethernet Exists
1.1Communication NetworksPlanned1.2LAN FundamentalsPlanned1.3Shared Media ChallengesPlanned1.4Packet SwitchingPlanned1.5Ethernet OriginsPlanned1.6Evolution of EthernetPlanned1.7Why Ethernet WonPlanned
Module 2
Ethernet Architecture Overview
2.1Ethernet Architecture OverviewPlanned2.2Layered NetworkingPlanned2.3The MAC LayerPlanned2.4The PHY LayerPlanned2.5SwitchesPlanned2.6RoutersPlanned2.7End SystemsPlanned
Module 3
OSI Model for Hardware Engineers
3.1Physical LayerPlanned3.2Data Link LayerPlanned3.3Network LayerPlanned3.4Transport LayerPlanned3.5Application LayerPlanned3.6Where Ethernet FitsPlanned
Module 4
Ethernet Physical Layer
4.1Copper EthernetPlanned4.2Fiber EthernetPlanned4.3Differential SignalingPlanned4.4Encoding BasicsPlanned4.5Link EstablishmentPlanned4.6PHY ResponsibilitiesPlanned
Module 5
MAC vs PHY
5.1MAC vs PHY OverviewPlanned5.2MAC ResponsibilitiesPlanned5.3PHY ResponsibilitiesPlanned5.4Data FlowPlanned5.5Link ManagementPlanned5.6Real RTL BoundariesPlanned
Module 6
Ethernet Frame Format
6.1Frame Format OverviewPlanned6.2PreamblePlanned6.3Start Frame Delimiter (SFD)Planned6.4Destination MACPlanned6.5Source MACPlanned6.6EtherType / LengthPlanned6.7PayloadPlanned6.8Frame Check Sequence (FCS)Planned
Module 7
MAC Addresses
7.1Address StructurePlanned7.2UnicastPlanned7.3MulticastPlanned7.4BroadcastPlanned7.5OUIPlanned7.6Address LearningPlanned
Module 8
CRC and FCS
8.1Why CRC ExistsPlanned8.2CRC GenerationPlanned8.3CRC CheckingPlanned8.4Error DetectionPlanned8.5RTL ImplementationPlanned
Module 9
Ethernet Speed Evolution
9.110 Mbps EthernetPlanned9.2100 Mbps (Fast Ethernet)Planned9.31G (Gigabit Ethernet)Planned9.410G EthernetPlanned9.525G EthernetPlanned9.640G EthernetPlanned9.7100G EthernetPlanned9.8200G EthernetPlanned9.9400G EthernetPlanned9.10800G EthernetPlanned
Module 10
MII Family of Interfaces
10.1MIIPlanned10.2RMIIPlanned10.3GMIIPlanned10.4RGMIIPlanned10.5SGMIIPlanned10.6XGMIIPlanned
Module 11
Auto-Negotiation
11.1Link DiscoveryPlanned11.2Speed NegotiationPlanned11.3Duplex NegotiationPlanned11.4Link Bring-UpPlanned11.5Failure CasesPlanned
Module 12
Half Duplex and Full Duplex
12.1CSMA/CD HistoryPlanned12.2Collision DetectionPlanned12.3Half DuplexPlanned12.4Full DuplexPlanned12.5Modern EthernetPlanned
Module 13
Ethernet Switching
13.1Switching OverviewPlanned13.2MAC LearningPlanned13.3ForwardingPlanned13.4FloodingPlanned13.5FilteringPlanned13.6Switching TablesPlanned13.7Unknown Destination HandlingPlanned
Module 14
VLANs
14.1Why VLANs ExistPlanned14.2VLAN TaggingPlanned14.3VLAN IDsPlanned14.4Trunk PortsPlanned14.5Access PortsPlanned14.6Enterprise NetworksPlanned
Module 15
Flow Control
15.1PAUSE FramesPlanned15.2CongestionPlanned15.3BackpressurePlanned15.4Data Center ImplicationsPlanned
Module 16
Jumbo Frames
16.1MTUPlanned16.2Jumbo FramesPlanned16.3Throughput BenefitsPlanned16.4Compatibility ChallengesPlanned
Module 17
Link Aggregation
17.1Multiple LinksPlanned17.2Load BalancingPlanned17.3RedundancyPlanned17.4LACP ConceptsPlanned
Module 18
Ethernet Timing
18.1LatencyPlanned18.2ThroughputPlanned18.3Serialization DelayPlanned18.4Propagation DelayPlanned18.5BufferingPlanned
Module 19
Precision Time Protocol (PTP)
19.1Precision Time Protocol OverviewPlanned19.2Why Time Synchronization MattersPlanned19.3IEEE 1588Planned19.4Master ClockPlanned19.5Slave ClockPlanned19.6TimestampingPlanned19.7Synchronization AccuracyPlanned
Module 20
Time-Sensitive Networking (TSN)
20.1Deterministic EthernetPlanned20.2SchedulingPlanned20.3Automotive NetworkingPlanned20.4Industrial ApplicationsPlanned
Module 21
Ethernet in SoCs
21.1The Ethernet MACPlanned21.2DMA EnginesPlanned21.3Descriptor RingsPlanned21.4AXI IntegrationPlanned21.5Interrupt HandlingPlanned
Module 22
Ethernet DMA Architecture
22.1RX DMAPlanned22.2TX DMAPlanned22.3Descriptor StructuresPlanned22.4Memory Access PatternsPlanned22.5Performance OptimizationPlanned
Module 23
Ethernet RTL Design
23.1MAC ArchitecturePlanned23.2Frame ParserPlanned23.3CRC EnginePlanned23.4DMA InterfacePlanned23.5FIFO DesignPlanned23.6Statistics CountersPlanned
Module 24
Ethernet Verification
24.1Packet GenerationPlanned24.2AssertionsPlanned24.3ScoreboardsPlanned24.4CoveragePlanned24.5Error InjectionPlanned24.6UVM Ethernet AgentPlanned
Module 25
Ethernet Debugging
25.1Ethernet Debugging OverviewPlanned25.2CRC ErrorsPlanned25.3Link FailuresPlanned25.4Negotiation FailuresPlanned25.5Packet DropsPlanned25.6DMA IssuesPlanned25.7Throughput ProblemsPlanned25.8Packet Capture AnalysisPlanned
Module 26
Ethernet in Data Centers
26.1Spine-Leaf NetworksPlanned26.2High-Speed LinksPlanned26.3AI ClustersPlanned26.4Cloud InfrastructurePlanned
Module 27
Ethernet in Automotive
27.1Automotive EthernetPlanned27.2TSN in AutomotivePlanned27.3ADAS SystemsPlanned27.4Autonomous DrivingPlanned
Module 28
Ethernet Interview Mastery
28.1Beginner QuestionsPlanned28.2Intermediate QuestionsPlanned28.3Advanced QuestionsPlanned28.4Senior QuestionsPlanned
Module 29
Ethernet vs Other Interconnects
29.1Ethernet vs PCIePlanned29.2Ethernet vs USBPlanned29.3Ethernet vs InfiniBandPlanned29.4Ethernet vs Proprietary FabricsPlanned
Module 30
Real Industry Case Studies
30.1Ethernet Switch ASICsPlanned30.2SmartNICsPlanned30.3Data Center NICsPlanned30.4Automotive ControllersPlanned30.5FPGA Ethernet DesignsPlanned30.6AI NetworkingPlanned
Module 31
Ethernet Design Review Checklist
31.1Architecture ChecklistPlanned31.2RTL ChecklistPlanned31.3Verification ChecklistPlanned31.4Performance ChecklistPlanned31.5Integration ChecklistPlanned31.6Debug ChecklistPlanned31.7Interview ChecklistPlanned
Module 32
Ethernet Misconceptions Engineers Have
32.1"Ethernet Equals TCP/IP"Planned32.2"MAC Addresses Are Globally Unique Forever"Planned32.3"CRC Provides Security"Planned32.4"VLANs Improve Performance Automatically"Planned32.5"Switches Eliminate Broadcasts"Planned32.6"Full-Duplex Ethernet Uses CSMA/CD"Planned