201Total chapters
34Modules
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Memory hierarchy first
Why SRAM is not enough, why DRAM exists, the memory wall, and the 1T1C-cell physics that produces every later DDR concept — the foundations the rest of the curriculum rides on.
Interview-ready depth
A dedicated interview module plus per-chapter interview weighting — tRCD, CAS latency, row-buffer hits / misses, controller scheduling, write leveling, performance tuning, silicon-bring-up debug.
Design → verify → debug
DDR controller (scheduler, queues, refresh) and PHY (training, DQS, calibration) RTL discipline, JEDEC-compliance verification, and trace-driven silicon debug — the full engineering loop.
DDR Complete Curriculum
Your Learning Roadmap
201 chapters · 34 modules — DRAM cell physics, controllers, PHY training, and DDR4 / DDR5 / LPDDR / HBM.
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Module 1
Why DRAM Exists
1.1The Memory HierarchyPlanned1.2RegistersPlanned1.3SRAMPlanned1.4DRAMPlanned1.5FlashPlanned1.6Cost vs DensityPlanned1.7Why DRAM Dominates Main MemoryPlanned1.8The Memory Wall ProblemPlanned
Module 2
DRAM Fundamentals
2.1Capacitor StoragePlanned2.2Charge Storage and LeakagePlanned2.3The Refresh RequirementPlanned2.4The DRAM Cell (1T1C)Planned2.5The Destructive-Read PropertyPlanned2.6Restore OperationsPlanned
Module 3
DRAM Array Architecture
3.1RowsPlanned3.2ColumnsPlanned3.3BitlinesPlanned3.4WordlinesPlanned3.5Sense AmplifiersPlanned3.6Memory Matrices and HierarchyPlanned
Module 4
DDR Evolution
4.1SDR SDRAMPlanned4.2DDR (DDR1)Planned4.3DDR2Planned4.4DDR3Planned4.5DDR4Planned4.6DDR5Planned4.7LPDDR EvolutionPlanned4.8HBM OverviewPlanned
Module 5
DDR Architecture Overview
5.1The DDR Device StructurePlanned5.2BanksPlanned5.3Bank GroupsPlanned5.4RanksPlanned5.5ChannelsPlanned5.6DIMMsPlanned5.7The Memory-Subsystem ViewPlanned
Module 6
DDR Signals
6.1CK / CK# — The Differential ClockPlanned6.2CKE — Clock EnablePlanned6.3CS# — Chip SelectPlanned6.4RAS# — Row Address StrobePlanned6.5CAS# — Column Address StrobePlanned6.6WE# — Write EnablePlanned6.7ODT — On-Die Termination ControlPlanned6.8RESET# — Asynchronous ResetPlanned6.9DQ — The Data BusPlanned6.10DQS — The Data StrobePlanned6.11DM — The Data MaskPlanned6.12Other Sideband SignalsPlanned
Module 7
DDR Commands
7.1Activate (ACT)Planned7.2Read (RD / RDA)Planned7.3Write (WR / WRA)Planned7.4Precharge (PRE / PREA)Planned7.5Refresh (REF)Planned7.6Mode-Register Set (MRS)Planned7.7ZQ Calibration (ZQCS / ZQCL)Planned
Module 8
DDR Addressing
8.1Row AddressPlanned8.2Column AddressPlanned8.3Bank AddressPlanned8.4Bank-Group AddressPlanned8.5Rank SelectionPlanned8.6Physical MappingPlanned
Module 9
Activate and Precharge
9.1Row OpeningPlanned9.2The Row BufferPlanned9.3Row HitsPlanned9.4Row MissesPlanned9.5Row ConflictsPlanned9.6Performance ImpactPlanned
Module 10
Read Operations
10.1The Read CommandPlanned10.2CAS Latency (CL)Planned10.3Data ReturnPlanned10.4Burst ReadsPlanned10.5Read Timing AnalysisPlanned
Module 11
Write Operations
11.1The Write CommandPlanned11.2Write Latency (CWL)Planned11.3Burst WritesPlanned11.4Write Recovery (tWR)Planned11.5Write Timing AnalysisPlanned
Module 12
Burst Operations
12.1Burst LengthPlanned12.2Sequential BurstPlanned12.3Interleaved BurstPlanned12.4Data-Transfer EfficiencyPlanned
Module 13
DDR Timing Fundamentals
13.1Why Timing Parameters ExistPlanned13.2Device Physics Behind TimingPlanned13.3Timing Constraints CataloguePlanned13.4Command SchedulingPlanned
Module 14
Key DDR Timing Parameters
14.1tRCD — RAS-to-CAS DelayPlanned14.2tRP — Row Precharge TimePlanned14.3tRAS — Row Active TimePlanned14.4tRC — Row Cycle TimePlanned14.5tWR — Write RecoveryPlanned14.6tCCD — CAS-to-CAS DelayPlanned14.7tRRD — Row-to-Row DelayPlanned14.8tFAW — Four-Activate WindowPlanned14.9CL — CAS LatencyPlanned14.10CWL — CAS Write LatencyPlanned
Module 15
Refresh Operations
15.1Why Refresh ExistsPlanned15.2Refresh CommandsPlanned15.3Refresh SchedulingPlanned15.4Retention TimePlanned15.5Refresh Bandwidth ImpactPlanned
Module 16
Banks and Bank Groups
16.1Bank-Level ParallelismPlanned16.2Bank-Aware SchedulingPlanned16.3Performance OptimisationPlanned16.4DDR4 / DDR5 Bank-Group ConceptsPlanned
Module 17
DDR Controller Architecture
17.1The Command SchedulerPlanned17.2The Command QueuePlanned17.3The Refresh ManagerPlanned17.4ArbitrationPlanned17.5Request HandlingPlanned
Module 18
Address Mapping
18.1Row-Bank-Column MappingPlanned18.2Mapping for PerformancePlanned18.3Spatial LocalityPlanned18.4Real-System ExamplesPlanned
Module 19
DDR PHY Fundamentals
19.1PHY ResponsibilitiesPlanned19.2SerialisationPlanned19.3Timing AlignmentPlanned19.4DQS HandlingPlanned19.5PHY CalibrationPlanned
Module 20
DQS and Data Capture
20.1Source-Synchronous InterfacesPlanned20.2The DQS ConceptPlanned20.3Read CapturePlanned20.4Write LevelingPlanned20.5Timing WindowsPlanned
Module 21
DDR Training
21.1Write Leveling AlgorithmPlanned21.2Read LevelingPlanned21.3Gate TrainingPlanned21.4Eye CenteringPlanned21.5Training AlgorithmsPlanned
Module 22
ODT and Signal Integrity
22.1On-Die TerminationPlanned22.2ReflectionsPlanned22.3Signal IntegrityPlanned22.4High-Speed EffectsPlanned
Module 23
DDR Performance
23.1DDR Latency AnatomyPlanned23.2DDR BandwidthPlanned23.3Row-Buffer LocalityPlanned23.4Scheduling OptimisationPlanned23.5Controller PoliciesPlanned
Module 24
LPDDR Fundamentals
24.1Mobile-Memory MissionPlanned24.2Low-Power FeaturesPlanned24.3LPDDR4 ArchitecturePlanned24.4LPDDR5 ArchitecturePlanned24.5Mobile-Power ManagementPlanned
Module 25
DDR5 Architecture
25.1DDR5 Bank-Group EnhancementsPlanned25.2Dual Sub-ChannelsPlanned25.3On-DIMM PMICPlanned25.4DDR5 New CapabilitiesPlanned
Module 26
HBM Fundamentals
26.1Why HBM ExistsPlanned26.22.5D Packaging for HBMPlanned26.3Through-Silicon Vias (TSVs)Planned26.4HBM for AI AcceleratorsPlanned
Module 27
DDR Verification
27.1JEDEC CompliancePlanned27.2DDR AssertionsPlanned27.3DDR MonitorsPlanned27.4DDR ScoreboardsPlanned27.5DDR Functional CoveragePlanned27.6DDR VIP UsagePlanned27.7UVM Architecture for DDRPlanned
Module 28
DDR Debugging
28.1Training FailuresPlanned28.2Timing ViolationsPlanned28.3Refresh IssuesPlanned28.4Calibration FailuresPlanned28.5Data CorruptionPlanned28.6Signal-Integrity ProblemsPlanned28.7DDR Silicon Bring-UpPlanned
Module 29
DDR in SoC Architecture
29.1AXI-to-DDR FlowPlanned29.2Memory Controllers in SoCsPlanned29.3CPU Access PatternsPlanned29.4DMA Access PatternsPlanned29.5Accelerator Access PatternsPlanned
Module 30
DDR Interview Mastery
30.1Why DRAM Refresh?Planned30.2Row-Buffer QuestionPlanned30.3tRCD QuestionPlanned30.4CAS-Latency QuestionPlanned30.5Controller-Scheduling QuestionPlanned30.6Training QuestionPlanned30.7PHY QuestionPlanned30.8Senior Performance TuningPlanned30.9Senior Verification StrategyPlanned30.10Senior Silicon DebugPlanned
Module 31
DDR vs Other Memories
31.1DDR vs SRAMPlanned31.2DDR vs LPDDRPlanned31.3DDR vs HBMPlanned31.4DDR vs GDDRPlanned
Module 32
Real Industry Case Studies
32.1CPU Memory ControllersPlanned32.2Mobile SoCsPlanned32.3GPUsPlanned32.4AI AcceleratorsPlanned32.5Data-Centre ServersPlanned
Module 33
DDR Design-Review Checklist
33.1Architecture Review ChecklistPlanned33.2RTL Review ChecklistPlanned33.3PHY Review ChecklistPlanned33.4Verification Review ChecklistPlanned33.5Performance Review ChecklistPlanned33.6Bring-Up Review ChecklistPlanned33.7Debug Review ChecklistPlanned33.8Interview Review ChecklistPlanned
Module 34
DDR Misconceptions Engineers Have
34.1“CAS Latency Equals Memory Latency”Planned34.2“Refresh Only Affects Idle Systems”Planned34.3“DDR Bandwidth Equals Application Bandwidth”Planned34.4“DDR Controller Is Simple Arbitration”Planned34.5“Training Happens Only Once”Planned34.6“DDR5 Is Just Faster DDR4”Planned