164Total chapters
31Modules
0Chapters live
0 / 31Active modules
Memory wall first
The memory wall, CPU-centric computing limits, accelerator explosion, data-movement costs — the engineering forces that produced CXL before a single protocol layer is named.
Interview-ready depth
A dedicated interview module plus per-chapter interview weighting — CXL.io vs .cache vs .mem, device-type selection, memory pooling, fabric architecture, coherency flows, silicon-bring-up debug.
Design → verify → debug
Protocol-engine / transaction / memory-controller / device RTL pipelines, SVA / UVM coherency verification, and trace-driven silicon debugging — the full engineering loop for a CXL link.
CXL Complete Curriculum
Your Learning Roadmap
164 chapters · 31 modules — coherent attach, CXL.io / .cache / .mem, type-1/2/3 devices, and memory pooling.
0of 164 chapters live
0% complete
Module 1
Why CXL Exists
1.1The Memory WallPlanned1.2CPU-Centric Computing LimitsPlanned1.3Data-Movement CostsPlanned1.4Accelerator GrowthPlanned1.5GPU Memory BottlenecksPlanned1.6PCIe LimitationsPlanned1.7Why Coherent Attach MattersPlanned
Module 2
CXL Overview
2.1What Is CXL?Planned2.2The CXL ConsortiumPlanned2.3Evolution of CXLPlanned2.4Relationship to PCIePlanned2.5Architectural GoalsPlanned
Module 3
CXL Architecture
3.1The CXL HostPlanned3.2The CXL DevicePlanned3.3The CXL FabricPlanned3.4Coherent Communication ModelPlanned3.5CXL Layered ArchitecturePlanned3.6The CXL System ViewPlanned
Module 4
The CXL Stack
4.1Physical LayerPlanned4.2Data Link LayerPlanned4.3Transaction LayerPlanned4.4The Three Protocol LayersPlanned4.5Relationship to the PCIe StackPlanned
Module 5
PCIe Foundation of CXL
5.1Why CXL Uses PCIePlanned5.2PCIe Reuse in CXLPlanned5.3CXL Link InitialisationPlanned5.4CXL Link TrainingPlanned5.5CXL DiscoveryPlanned5.6PCIe / CXL CompatibilityPlanned
Module 6
The CXL Protocol Family
6.1The Three CXL ProtocolsPlanned6.2Protocol InteractionsPlanned6.3Protocol Use-Case TaxonomyPlanned6.4Protocol Selection DisciplinePlanned
Module 7
CXL.io
7.1CXL.io OverviewPlanned7.2Configuration Over CXL.ioPlanned7.3Management Over CXL.ioPlanned7.4Discovery Over CXL.ioPlanned7.5CXL.io ↔ PCIe TransactionsPlanned
Module 8
CXL.cache
8.1CXL.cache OverviewPlanned8.2Host Cache AccessPlanned8.3Device Cache AccessPlanned8.4Coherent AcceleratorsPlanned8.5Cache Ownership TransferPlanned
Module 9
CXL.mem
9.1CXL.mem OverviewPlanned9.2Host Access to Device MemoryPlanned9.3Memory-Expansion SemanticsPlanned9.4CXL.mem Read FlowsPlanned9.5CXL.mem Write FlowsPlanned9.6CXL.mem Performance ImplicationsPlanned
Module 10
CXL Device Types
10.1Type 1 DevicesPlanned10.2Type 2 DevicesPlanned10.3Type 3 DevicesPlanned10.4Device-Type Selection DisciplinePlanned
Module 11
Memory Expansion
11.1Why Memory Expansion MattersPlanned11.2Capacity ScalingPlanned11.3Memory Resource SharingPlanned11.4Server ArchitecturesPlanned11.5AI Workloads on Expanded MemoryPlanned
Module 12
Memory Pooling
12.1Shared Memory PoolsPlanned12.2Resource AllocationPlanned12.3Multi-Host SystemsPlanned12.4Datacenter ArchitecturePlanned12.5Memory-Pooling Benefits and ChallengesPlanned
Module 13
Coherency Fundamentals
13.1Cache Coherency ReviewPlanned13.2Shared Memory Across CXLPlanned13.3Ownership in CXLPlanned13.4State ManagementPlanned13.5Relationship to CHIPlanned
Module 14
CXL Coherency Flows
14.1Coherent Read FlowsPlanned14.2Coherent Write FlowsPlanned14.3Ownership-Transfer FlowsPlanned14.4Cache-Interaction FlowsPlanned14.5State TransitionsPlanned
Module 15
Fabric Architecture
15.1Fabric ManagersPlanned15.2Fabric TopologiesPlanned15.3Resource DiscoveryPlanned15.4Dynamic Resource AllocationPlanned15.5Future Datacentres on CXLPlanned
Module 16
CXL Switches
16.1CXL Switch ArchitecturePlanned16.2Switch RoutingPlanned16.3Switch Resource SharingPlanned16.4Switch ScalabilityPlanned
Module 17
CXL Memory Devices
17.1Memory ExpandersPlanned17.2Persistent-Memory DevicesPlanned17.3Future Memory SystemsPlanned17.4Real Industry Memory DevicesPlanned
Module 18
CXL Performance
18.1CXL Latency AnatomyPlanned18.2CXL ThroughputPlanned18.3Memory-Access CostPlanned18.4Fabric ScalingPlanned18.5Performance-Analysis DisciplinePlanned
Module 19
CXL Security
19.1Device AuthenticationPlanned19.2Secure CommunicationPlanned19.3IsolationPlanned19.4Multi-Tenant EnvironmentsPlanned
Module 20
CXL 2.0
20.1CXL 2.0 SwitchingPlanned20.2CXL 2.0 Memory PoolingPlanned20.3CXL 2.0 Architectural ChangesPlanned20.4CXL 2.0 New CapabilitiesPlanned
Module 21
CXL 3.0
21.1CXL 3.0 Fabric EnhancementsPlanned21.2CXL 3.0 Peer-to-PeerPlanned21.3CXL 3.0 ScalabilityPlanned21.4The CXL 3.x Future VisionPlanned
Module 22
CXL in AI Systems
22.1CXL with AI AcceleratorsPlanned22.2Memory Expansion for AIPlanned22.3CXL in GPU SystemsPlanned22.4CXL for Large Language ModelsPlanned22.5AI Training ClustersPlanned
Module 23
CXL in Data Centres
23.1Memory DisaggregationPlanned23.2Composable InfrastructurePlanned23.3Resource UtilisationPlanned23.4Cloud Architectures on CXLPlanned
Module 24
CXL RTL Design Thinking
24.1CXL Protocol EnginesPlanned24.2Transaction ProcessingPlanned24.3CXL Memory ControllersPlanned24.4Device ArchitecturePlanned24.5Buffering StrategiesPlanned
Module 25
CXL Verification
25.1CXL Protocol VerificationPlanned25.2Coherency VerificationPlanned25.3CXL AssertionsPlanned25.4CXL ScoreboardsPlanned25.5CXL Functional CoveragePlanned25.6CXL VIP UsagePlanned25.7UVM Architecture for CXLPlanned
Module 26
CXL Debugging
26.1Discovery FailuresPlanned26.2Link FailuresPlanned26.3Coherency BugsPlanned26.4Memory-Access IssuesPlanned26.5Fabric ProblemsPlanned26.6Performance BottlenecksPlanned26.7CXL Silicon DebugPlanned
Module 27
CXL Interview Mastery
27.1What Is CXL?Planned27.2CXL.io QuestionPlanned27.3CXL.cache QuestionPlanned27.4CXL.mem QuestionPlanned27.5Memory-Pooling QuestionPlanned27.6Device-Type QuestionPlanned27.7Fabric-Architecture QuestionPlanned27.8Senior Coherency QuestionPlanned27.9Senior Verification QuestionPlanned27.10Senior Debugging QuestionPlanned
Module 28
CXL vs Other Interconnects
28.1CXL vs PCIePlanned28.2CXL vs CHIPlanned28.3CXL vs UCIePlanned28.4CXL vs Proprietary FabricsPlanned
Module 29
Real Industry Case Studies
29.1AI Training ClustersPlanned29.2Memory Expansion CardsPlanned29.3Cloud Data CentresPlanned29.4GPU Memory SharingPlanned29.5Composable InfrastructurePlanned
Module 30
CXL Design-Review Checklist
30.1Architecture Review ChecklistPlanned30.2RTL Review ChecklistPlanned30.3Verification Review ChecklistPlanned30.4Coherency Review ChecklistPlanned30.5Performance Review ChecklistPlanned30.6Integration Review ChecklistPlanned30.7Debug Review ChecklistPlanned30.8Interview Review ChecklistPlanned
Module 31
CXL Misconceptions Engineers Have
31.1“CXL Replaces PCIe”Planned31.2“CXL Is Only for Memory”Planned31.3“CXL.cache and CXL.mem Are Identical”Planned31.4“Memory Pooling Is Just Virtualisation”Planned31.5“CXL Automatically Solves Coherency”Planned31.6“Only Hyperscalers Need CXL”Planned