All GLS labs
GLS Lab
Lab 32of 50
GLS Fundamentals and Simulation Setup10
- 1Why RTL Passes but GLS Fails
- 2Generating a Gate-Level Netlist
- 3A GLS Testbench for a Synthesized Netlist
- 4Standard-Cell Models in GLS
- 5Comparing RTL and Zero-Delay GLS
- 6Netlist Elaboration Errors
- 7Reset and Initialization: RTL vs GLS
- 8X and Z Propagation Through a Netlist
- 9Debugging an RTL-vs-GLS Waveform Mismatch
- 10A Reproducible RTL-versus-GLS Regression
RTL Coding Techniques and Synthesis Behavior10
- 11Blocking vs Nonblocking Assignments in GLS
- 12Detecting Inferred Latches
- 13Incomplete Case Statements After Synthesis
- 14FSM Encoding and Transitions After Synthesis
- 15Reset Polarity and Reset-Release Defects
- 16Asynchronous- and Synchronous-Reset Flip-Flops
- 17X from Partially Initialized Registers
- 18Clock-Enable and Conditional Register Updates
- 19Unintended Priority Logic and Timing Depth
- 20Width and Signedness Mismatches
Timing-Aware GLS and SDF Annotation10
- 21Annotating SDF onto a Netlist
- 22Missing or Incorrect SDF Annotations
- 23Minimum, Typical and Maximum Delays
- 24Creating and Diagnosing a Setup Violation
- 25Creating and Diagnosing a Hold Violation
- 26Clock Skew, Propagation Delay and Captured Data
- 27Recovery and Removal Violations
- 28Glitches from Unequal Path Delays
- 29Pulse-Width Violations and Notifiers
- 30Correlating SDF Failures with STA
Advanced GLS Verification and Debugging10
- 31Avoiding Sampling Races in GLS Testbenches
- 32Clocking Blocks for Gate-Level Outputs
- 33Ready/Valid Handshakes with Gate Delays
- 34FIFO Behavior at Gate Level
- 35Real X Defects vs Modeling Artifacts
- 36Asynchronous-Reset Release Near a Clock Edge
- 37A CDC Failure Exposed by GLS
- 38Clock Gating with Realistic Timing
- 39Assertions and Scoreboards Without False Failures
- 40Isolating a Failing Transaction in a Large Regression
Industry-Style GLS Debugging and Signoff10
- 41A GLS Failure from an Incorrect Reset Sequence
- 42Power-On Initialization Assumptions
- 43Multi-Cycle Datapaths and Timing Constraints
- 44Timing Failure at a Pipeline Boundary
- 45Functional Mismatches vs SDF-Induced Failures
- 46Automated GLS Regression with Structured Reporting
- 47RTL, Netlist and Testbench Assumption Mismatches
- 48A Small APB Peripheral at Gate Level
- 49GLS Review of a FIFO-Based Subsystem
- 50End-to-End RTL-to-GLS Signoff
GLS-032Advanced GLS Verification and DebuggingPublished
Clocking Blocks for Gate-Level Outputs
How do you use SystemVerilog clocking blocks to sample gate-level outputs safely?
Advanced~105 min
Concepts covered
- Clocking blocks
- Input / output skew
- Safe sampling
This lab is part of the GLS Lab
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