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DFT Design & Verification Labs
Lab 19of 50
DFT Fundamentals & Testability10
- 1Build a Combinational Circuit and Evaluate Its Testability
- 2Detect Stuck-at-0 and Stuck-at-1 Faults
- 3Analyze Controllability and Observability in RTL
- 4Design a Fault Injection Testbench
- 5Measure Fault Coverage for a Small RTL Block
- 6Verify Reset and Initialization Testability
- 7Design a Testable Register Bank
- 8Analyze Unknown-State Propagation
- 9Verify Functional and Test Mode Isolation
- 10Build a Mini RTL Testability Assessment
Scan Architecture & RTL Implementation10
- 11Design and Verify a Scan-Enabled D Flip-Flop
- 12Convert a Register Bank into a Scan Chain
- 13Verify Scan Shift Operations
- 14Implement Scan Capture and Shift Sequences
- 15Design and Verify Scan Enable Control
- 16Implement Multiple Scan Chains
- 17Verify Scan Chain Length and Connectivity
- 18Build a Scan Chain Integrity Checker
- 19Analyze Scan Chain Timing Assumptions
- 20Build a Parameterized Scan Register Module
ATPG, Fault Models & Coverage10
- 21Generate Test Vectors for Combinational Stuck-at Faults
- 22Develop a Fault Simulation Engine
- 23Implement a Simplified D-Algorithm Exercise
- 24Generate ATPG Patterns for a Sequential Scan Design
- 25Analyze Undetected and Redundant Faults
- 26Implement Transition-Fault Test Patterns
- 27Verify Launch-on-Capture Test Sequences
- 28Verify Launch-on-Shift Test Sequences
- 29Build a Fault Coverage Report Generator
- 30Optimize ATPG Pattern Count
MBIST, BIST & Test Infrastructure10
- 31Design a March-Based Memory Test Controller
- 32Verify March C- Memory Test Operations
- 33Inject Memory Faults and Verify Detection
- 34Design a Linear Feedback Shift Register
- 35Build a Pseudorandom Logic BIST Pattern Generator
- 36Implement a Multiple Input Signature Register
- 37Design a Complete Logic BIST Controller
- 38Analyze BIST Signature Aliasing
- 39Implement a Simplified JTAG TAP Controller
- 40Verify JTAG Instruction and Data Register Access
Advanced DFT Integration & Verification10
- 41Design a Multi-Clock Scan Test Architecture
- 42Verify a Test Clock Controller
- 43Analyze Scan Chain Clock-Domain Crossing Risks
- 44Design and Verify a Scan Compression Model
- 45Verify X-Masking in Scan Response Compaction
- 46Build a DFT Assertion-Based Verification Suite
- 47Develop a Reusable DFT Verification Environment
- 48Debug a Faulty Scan Architecture
- 49Verify Functional-to-Test Mode Integration
- 50Capstone: Design and Verify a DFT-Enabled RTL Subsystem
DFT-19Scan Architecture & RTL ImplementationPublished
Analyze Scan Chain Timing Assumptions
Identify the timing assumptions a zero-delay scan simulation hides — hold on short scan paths, lock-up latches across clock edges — and state which need static timing analysis rather than RTL simulation.
Intermediate~60 min
Concepts covered
- Shift hold time
- Lock-up latches
- Simulation vs STA
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