8.6 inheritance | VLSI Mentor

8.6. Introduction to Inheritance

8.6.1 What is Inheritance?

Inheritance is a mechanism where a new class (called derived class or child class) is created from an existing class (called base class or parent class). The derived class inherits all properties and methods from the base class and can also add new features or modify existing ones.

Benefits of Inheritance:

Code Reusability: Write code once, use it in multiple classes

Easy Maintenance: Changes in base class automatically reflect in derived classes

Extensibility: Add new features without modifying existing code

Hierarchical Classification: Organize classes in a logical manner

8.6.2. Types of Inheritance in SystemVerilog

SystemVerilog supports three types of inheritance:

Single Inheritance

Multilevel Inheritance

Hierarchical Inheritance

NOTE: SystemVerilog does NOT support Multiple Inheritance (where a class inherits from more than one base class). This design choice prevents the Diamond Problem and keeps the language simpler.

8.6.2.1 Single Inheritance

Single inheritance is when a derived class inherits from only one base class. This is the simplest and most common form of inheritance.

Example: Single Inheritance

Explanation: The EthernetPacket class extends the Packet class, inheriting header, payload, and display() method. It also adds its own property (mac_address) and method (show_mac()).

8.6.2.2 Multilevel Inheritance

Multilevel inheritance is when a class is derived from another derived class, creating a chain of inheritance. This forms a hierarchy:

GrandParent → Parent → Child

Example: Multilevel Inheritance

Verilog

Explanation: BurstReadTransaction inherits from ReadTransaction, which in turn inherits from Transaction. The final class has access to all properties and methods from all three levels.

8.6.2.3 Hierarchical Inheritance

Hierarchical inheritance is when multiple derived classes inherit from the same base class. This is useful when you have different types of objects that share common properties but have their own specific features.

Example: Hierarchical Inheritance

Verilog

Explanation: AHBTransaction, AXITransaction, and APBTransaction all inherit from the common base class BusTransaction, but each adds its own protocol-specific properties and methods.

8.6.3. Base Class and Derived Class Concepts

Understanding the relationship between base and derived classes is fundamental to inheritance.

Base Class (Parent Class)

A base class is the original class from which other classes are derived. It contains:

Common properties (data members)

Common methods (functions and tasks)

Constructor (new() function)

Derived Class (Child Class)

A derived class inherits from a base class using the 'extends' keyword. It:

Inherits all properties and methods from the base class

Can add new properties and methods

Can override methods from the base class

Must call the base class constructor using super.new()

Syntax for Creating Derived Classes

Verilog

8.6.4. Method Overriding

Method overriding allows a derived class to provide its own implementation of a method that is already defined in the base class. This is a key feature of polymorphism.

What is Method Overriding?

Method overriding happens when:

The derived class has a method with the same name as the base class method

The method has the same signature (same parameters and return type)

The derived class method replaces the base class method

Example: Method Overriding

Verilog

Output:

This is a vehicle: Generic Vehicle

This is a car: Sedan with 4 doors

8.6.5. Calling Base Class Method from Overridden Method

You can call the base class method from the overridden method using super.method_name():

Verilog

8.6.6. Real-World VLSI Verification Examples

Example 1: UVM Sequence Hierarchy

In UVM (Universal Verification Methodology), sequences use inheritance extensively:

Verilog

Example 2: Bus Protocol Abstraction

Verilog

Example 3: Coverage Model Hierarchy

Verilog

8.6.7. Common Pitfalls and How to Avoid Them

Pitfall 1: Forgetting super.new()

Problem: If you forget to call super.new() in the derived class constructor, base class members won't be initialized.

Verilog

Solution: Always call super.new() as the first statement in derived class constructor.

Pitfall 2: Not Using Virtual for Polymorphism

Problem: Without the virtual keyword, polymorphism won't work correctly.

Verilog

Solution: Use virtual keyword in base class for methods that should support polymorphism.

Pitfall 3: Accessing Private Members

Problem: Trying to access local (private) members from derived class.

Verilog

Solution: Use protected instead of local if you want derived classes to access the member.

Pitfall 4: Incorrect Parameter Passing to super.new()

Problem: Not passing required parameters to base class constructor.

Verilog

Solution: Pass correct parameters to super.new() matching base class constructor signature.

Pitfall 5: Type Mismatch in Polymorphism

Problem: Assigning incompatible types.

Verilog

Solution: Only assign derived class objects to base class handles, not between sibling classes.

Pitfall 6: Shallow Copy Issues

Problem: When copying objects with inheritance, only base class members get copied by default.

Solution: Override the copy() method in derived classes to ensure all members are copied correctly.

8.6.8. Coding Guidelines and Best Practices

8.6.8.1 Naming Conventions

Use descriptive class names: Transaction, not Txn

Base classes: Use generic names (Transaction, Packet)

Derived classes: Use specific names (AXITransaction, EthernetPacket)

Use consistent naming across hierarchy

8.6.8.2 Constructor Guidelines

Always call super.new() as the first statement

Initialize all class members in the constructor

Use meaningful parameter names

Document constructor parameters

8.6.8.3 Access Specifier Guidelines

Default to public unless there's a reason not to

Use protected for members that derived classes need to access

Use local (private) for implementation details

Never make frequently-changing members local - use protected instead

8.6.8.4 Virtual Method Guidelines

Use virtual for any method that might be overridden

Declare virtual in base class only, not in derived classes

Consider making display/print methods virtual

Use pure virtual for abstract base classes

8.6.8.5 Inheritance Depth Guidelines

Keep inheritance hierarchies shallow (3-4 levels maximum)

Deep hierarchies (>5 levels) become hard to understand and maintain

Consider composition over inheritance when hierarchy gets too deep

8.6.8.6 Documentation Guidelines

Document the purpose of each class

Document inheritance relationships

Explain why methods are virtual

Document any assumptions about derived classes

8.6.8.7 Code Example: Well-Structured Inheritance

Verilog

parameterized class

Encapsulation