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8.1. Overview - Class Fundamentals

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A class is a template that defines both data and the operations that can be performed on that data. It's the fundamental building block of object-oriented programming.

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​8.1.1. Key Terminology

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Class

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The definition or blueprint that describes what objects of this type will contain.

class Transaction;  // This is the class definition

    int id;

endclass

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Object

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An actual instance created from a class. Also called "class instance".

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Transaction t;  // Declare handle

t = new();      // Create object

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Handle

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A variable that points to an object. Think of it as a reference or pointer.

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Transaction t1, t2;  // Two handles

t1 = new();          // t1 points to object

t2 = t1;             // t2 points to same object

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Property (Data Member)

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Variables declared inside a class.

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class Example;

    int count;        // Property

    string name;      // Property

endclass

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Method

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Functions or tasks declared inside a class.

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class Example;

    function void print();  // Method

        $display("Example");

    endfunction

endclass

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​8.1.2. Syntax – Class Definition

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The Basic syntax for defining a class in SystemVerilog. 

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A class have two kinds of properties:

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  1. Data Members (Variables)

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 2.Methods (Tasks & Functions)

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Inbuilt Methods:

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  1. pre_randomize()

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 2. post_randomize()

 

 3. randomize()

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 4. new() – Constructor

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 5. constraint()

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 6. constraint_mode()

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 7. rand_mode()

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Basic Structure

Verilog

Complete Transaction Example

Verilog

8.1.3. Objects (Class Instance)

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Comprehensive coverage of objects (class instance) with practical examples.

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  • Creating objects with new()

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  • Handle vs object concept

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  • Multiple objects example

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  • Null handles

Verilog

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Real Example

Verilog

8.1.4. Four Pillars of OOPs

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1. Encapsulation

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Bundling data and methods together, hiding implementation details.

Verilog

2. Inheritance

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Create new classes based on existing classes.

Verilog

3. Polymorphism

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Objects of different types can be used through the same interface.

Verilog

4. Abstraction

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Hiding complex implementation, showing only essential features.

Verilog

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