8.3. Meaning of “static” and “automatic” in SV
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automatic
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Means new storage is created each time the code runs.
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Used mostly with tasks/functions.
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Variables are not shared between calls.
​
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Each call gets its own independent copy.
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Example – 1 : Automatic variable with “automatic” Keyword
Verilog
Output:
​
temp = 1
temp = 1
temp = 1
temp = 1
temp = 1
Example – 2 : Variable declaration inside automatic task
Verilog
Output:
​
x = 1
x = 1
x = 1
x = 1
x = 1
Example – 3 : Automatic Variable inside static task
Verilog
Output:
​
x = 1
x = 1
x = 1
x = 1
x = 1
Example – 4 : Static variable with no Keyword inside task of Class
Verilog
Output:
​
x = 1
x = 1
x = 1
x = 1
x = 1
​
static
​
-
Means single shared storage is used.
​
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Value is retained between calls.
​
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Same variable is shared across all calls/objects depending on context
Example – 1 : Static variable with no Keyword
Verilog
Output:
​
temp = 1
temp = 2
temp = 3
temp = 4
temp = 5
Example – 2 : Static variable with no Keyword inside task
Verilog
Output:
​
x = 1
x = 2
x = 3
x = 4
x = 5
Example – 3 : Static variable with static Keyword inside automatic task
Verilog
Output:
​
x = 1
x = 2
x = 3
x = 4
x = 5
Example – 4 : Static variable with static Keyword inside static task of Class
Verilog
Output:
​
x = 1
x = 2
x = 3
x = 4
x = 5