8.4. Copy Mechanism
​
First Understand : Class Variables are HANDLES
​
In SystemVerilog:
Packet p;​ // “p” is NOT an object.​
It is only a handle (pointer/reference).
​
Object is created only after:​
p = new();
​
What is Copy Mechanism in SystemVerilog?​
Copy mechanism means creating another variable/object which has same values as original.
​
There are three common cases:​
8.4.1. Handle Copy or Assignment (Reference Copy)
Verilog
Output:​
b2 = '{data:'ha, addr:'hf, mem:'{3, 4, 5, 7, 6, 2, 3, 45, 8, 54, 23, 23, 43, 45, 65, 75} , a:{ ref to class A}}, b2.a.i = 5
b1 = '{data:'h14, addr:'h3, mem:'{3, 4, 5, 7, 6, 2, 3, 45, 8, 54, 23, 23, 43, 45, 65, 75} , a:{ ref to class A}}, b1.a.i = 10
8.4.2. Shallow Copy (New Object, but nested objects shared)
.png)
Verilog
8.4.3. Deep Copy (New Object, Full Independent Duplicate)
Verilog
8.4.3. Deep Copy (New Object, Full Independent Duplicate)
.png)
Verilog
8.4.4. Copying Dynamic Arrays (Important for Transactions)
​
Dynamic arrays are NOT class handles, but copying rules are important.
Verilog
Output:
[p1] payload = aa bb cc dd
[p2] payload = 11 bb cc dd
8.4.5. Twisted Interview Example (Handle Copy + Deep Copy Mixed)
Verilog
8.4.6. Best Practice: copy() and clone() Style (UVM-like)
​
copy() - copies data into existing object
clone() - returns a new object
Verilog
8.4.7. Copy with Inheritance
​
Derived copy must call super.copy().
Verilog