8. General - Introduction to Object-Oriented Programming
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Classes are the foundation of object-oriented programming (OOP) in SystemVerilog. While modules and interfaces describe hardware structure, classes are used primarily in verification environments to create flexible, reusable, and maintainable testbench code.
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Think of a class as a cookie cutter, and objects as the cookies. You design the cookie cutter once (the class), and then you can make many cookies (objects) from it. Each cookie has the same shape but can have different decorations (property values).
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What is Object-Oriented Programming?
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OOP is a programming paradigm that organizes code around "objects" rather than just functions and variables. Each object combines data (properties) and the functions that work with that data (methods).
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Why Classes Matter in Verification?
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Organization - Group related data and behavior together
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Reusability - Write code once, use it many times
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Modularity - Break complex testbenches into manageable pieces
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Abstraction - Hide complex details, show only what's needed
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Inheritance - Build new functionality on top of existing code
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Polymorphism - Write flexible code that works with different types
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Real-World Verification Scenario
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Imagine you're verifying a PCIe controller. You need to:
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Generate hundreds of different transactions
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Send them to the DUT (Device Under Test)
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Collect responses
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Check if responses are correct
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Track which scenarios were tested
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Without classes, you would have:
Verilog
With classes, you have:
Verilog
Classes vs Modules vs Structures
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Understanding the differences:
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Modules
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Describe hardware (synthesizable)
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Cannot be created dynamically
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Used for RTL design
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Example: Adders, counters, state machines
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Structures (struct)
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Group related data
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Limited functionality
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Can be synthesized
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Example: Register fields, packet headers
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Classes
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Verification only (not synthesizable)
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Can be created dynamically with new()
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Support inheritance and polymorphism
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Example: Transactions, drivers, monitors, scoreboards
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Simple First Example
Verilog
Classes in UVM
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The Universal Verification Methodology (UVM) is built entirely on SystemVerilog classes. When you learn classes, you're learning the foundation of modern verification.
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uvm_component - Base class for all testbench components
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uvm_transaction - Base class for all transactions
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uvm_driver - Sends transactions to DUT
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uvm_monitor - Observes DUT activity
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uvm_scoreboard - Checks correctness
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Note: Classes are ONLY for verification (testbenches). They cannot be synthesized into hardware. Use modules and always blocks for RTL design.
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Tip: Start with simple classes and gradually add features. Don't try to use all OOP features at once!