Process Statement block:
Sequential Statement
In VHDL, a process statement is a block where the code is executed in a sequential order, meaning one line after another just like in a normal programming language. This block has a sensitivity list, which contains the signals that the output depends on. Whenever any of those signals change, the process is triggered again. That is why it is called a sensitivity list, because the output is sensitive to those inputs. In Verilog, the same idea is represented by the always block, which also runs whenever the signals in its sensitivity list change.
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On every rising edge of the clock, if reset is high the counter becomes zero, otherwise it increases by one.
VHDL
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
q <= 0;
else
q <= q + 1;
end if;
end if;
end process;
Verilog
always @(posedge clk) begin
if (reset)
q <= 0;
else
q <= q + 1;
What about delta delay in Sequential statements?
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In VHDL, delta delay is important both in sequential code (inside processes) Sequential statements (inside a process)
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When you write code inside a process, statements are executed one after another, step by step.
Example:
process(clk)
begin
b <= a; -- scheduled after one delta delay
c <= b; -- scheduled after the next delta delay
end process;
If a changes, the simulator first schedules b to update after a delta delay, and then schedules c to update after another delta delay.
This ordering ensures that c doesn’t get the “old” value of b by mistake.
Important Tip: Myth vs Fact
Many students think that a process statement always means sequential logic and therefore the clock must always be in the sensitivity list. This is not true.
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A process in VHDL simply means that the code inside it runs sequentially, one line after another. Whether the process creates combinational logic or sequential logic depends on what signals are in the sensitivity list and how the code is written.
If we write a process with only input signals in the sensitivity list and without a clock, it will create combinational logic.
For example, a multiplexer can be described like this:
Example:
process(a, b, sel)
begin
if sel = '1' then
y <= a;
else
y <= b;
end if;
end process;
Here, no clock is used. The output y updates immediately when a, b, or sel changes. This is pure combinational logic.
But if we include a clock in the sensitivity list and write code on the rising edge of the clock, then the process creates sequential logic like a D flip-flop.
Example:
process(clk, reset)
begin
if reset = '1' then
q <= '0';
elsif rising_edge(clk) then
q <= d;
end if;
end process;
Here, the output q updates only on the clock edge. This is sequential logic (flip-flop).
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So the truth is that a process can describe both combinational logic (like MUX) and sequential logic (like D flip-flop). The presence of the clock in the sensitivity list depends on what kind of logic we want to design.
Question:
Can you write the code for a 4-bit synchronous Serial in Serial out shift register that shifts all 4 bits in a single clock cycle? This may not be practical in real hardware, but it is important for your understanding.