Behavioral Modeling
What is Behavioral Modeling:
-
Behavioral modeling is called “behavioral” because it shows how the circuit behaves for different inputs.
-
In this style, we do not describe the internal structure or which gates are connected.
-
We only write the rules or conditions of the circuit, like if both inputs are 1, output is 1; otherwise output is 0.
-
The focus is on functionality, not on how it is built.
-
The actual gate-level implementation is decided later by the synthesis tool.
​
That’s why this style is called behavioral modeling.
An Analogy
​
Imagine you have a fan remote:
-
If you press 1, the fan runs slowly.
-
If you press 2, the fan runs a bit faster.
-
If you press 3, the fan runs even faster.
-
If you press 0, the fan stops.
​
Here you are only saying what happens when you press each button. You are not explaining how the remote is built inside, which chips or wires it uses, or how the motor is connected.
​
This is the idea of behavioral modeling: you describe only the behavior (the rules), not the inner structure.
Why Behavioral modelling:
In an 8×1 multiplexer, we are only interested in its functionality.
We do not care which gates are used inside or how they are connected.
What really matters is: for every value of the input select lines, which input should appear at the output.
​
That is why this is called behavioral modeling: we describe the behavior (rules), not the internal structure.
​
Here we use a case statement inside a process. The case directly tells us the output for each input condition.
Behavioral modeling is used when we know the functionality of a circuit and we know which inputs and outputs that functionality depends on.
We don’t need to worry about what is happening inside the “black box,” because the EDA tool will take care of that part for us.
Most designs are written in this style, because the designer only needs to understand the functional specification and how the system should work.
An important point is that behavioral code is written inside a process statement, which has a sensitivity list containing the inputs that can change the output.
​
How we use Behaviour Modelling :
Verilog
library ieee;
use ieee.std_logic_1164.all;
entity mux8x1 is
port (
sel : in std_logic_vector(2 downto 0); -- 3-bit select input
i0 : in std_logic;
i1 : in std_logic;
i2 : in std_logic;
i3 : in std_logic;
i4 : in std_logic;
i5 : in std_logic;
i6 : in std_logic;
i7 : in std_logic;
y : out std_logic
);
end entity mux8x1;
architecture behavioral of mux8x1 is
begin
process(sel, i0, i1, i2, i3, i4, i5, i6, i7)
begin
case sel is
when "000" => y <= i0;
when "001" => y <= i1;
when "010" => y <= i2;
when "011" => y <= i3;
when "100" => y <= i4;
when "101" => y <= i5;
when "110" => y <= i6;
when "111" => y <= i7;
when others => y <= '0'; -- default (safety)
end case;
end process;
end architecture;
The syntax of the case statement in VHDL is very similar to the switch–case in C language.
The difference is:
​
-
When there are many inputs, using if–else creates a nested structure of MUXes. This increases propagation delay, because the output has to pass through several levels of logic.
-
With a case statement, the tool creates a single multiplexer, which is faster and has less delay.
-
In an if–else chain, the first condition has higher priority, and the tool checks them one by one.
-
In a case statement, all options are considered equally, so the output can be decided more efficiently.
That is why case statements are often preferred when the design has many inputs.
​
Note: The synthesizer may still optimize both if–else and case into the same hardware, depending on the situation. But conceptually, case is more balanced (no priority), and if–else is priority-based.
Understanding the Case Statement with a MUX
Here, we only care about the functionality of the MUX and its inputs.
​
A multiplexer can be written in two ways:
​​
-
Using if–else statements
-
Using a case statement
1. In VHDL semantics
-
Both if–else and case are sequential statements.
-
That means they are executed one at a time by the simulator, inside a process.
So no statement in VHDL literally checks all conditions “at the same time.”
2. The real difference
-
If–else chain: conditions are evaluated in order. The first true branch is taken, others are skipped. → This creates priority logic in hardware.
-
Case statement: the value of the selector signal is matched against all choices, but only one choice can match. → There is no built-in priority — all cases are treated equally.
3. Why teachers/books sometimes say “case checks all inputs at once”
This is a way to explain the hardware meaning:
-
An if–else chain synthesizes into a priority multiplexer (signals pass through levels of gates).
-
A case statement synthesizes into a balanced multiplexer (all choices feed one selector circuit).
So in the circuit sense, the tool can generate a design where all input lines are connected to one MUX block, and the select line chooses among them “in parallel.”
​
Both if–else and case are sequential statements in VHDL, so they run one after another inside a process. The difference is that if–else gives priority to the first true condition, while case treats all choices equally. In hardware, this means if–else creates priority logic, and case creates a regular balanced multiplexer.
​
In VHDL, both if–else and case run sequentially inside the process. But when synthesized into hardware, if–else usually creates priority logic, which may look like nested 2×1 multiplexers. Case creates a balanced multiplexer where all inputs are equal choices. So the idea of ‘nested mux’ applies to the hardware generated by if–else, not to the simulation itself.
Verilog
library ieee;
use ieee.std_logic_1164.all;
entity mux4_if is
port (
sel : in std_logic_vector(1 downto 0); -- select lines (MSB = sel(1))
i0 : in std_logic;
i1 : in std_logic;
i2 : in std_logic;
i3 : in std_logic;
y : out std_logic
);
end entity mux4_if;
architecture behavioral of mux4_if is
begin
process(sel, i0, i1, i2, i3)
begin
if sel = "00" then
y <= i0;
elsif sel = "01" then
y <= i1;
elsif sel = "10" then
y <= i2;
else
y <= i3; -- when "11" or others treated as i3
end if;
end process;
end architecture behavioral;
HARDWARE:
Verilog
library ieee;
use ieee.std_logic_1164.all;
entity mux4_case is
port (
sel : in std_logic_vector(1 downto 0); -- select lines
i0 : in std_logic;
i1 : in std_logic;
i2 : in std_logic;
i3 : in std_logic;
y : out std_logic
);
end entity mux4_case;
architecture behavioral of mux4_case is
begin
process(sel, i0, i1, i2, i3)
begin
case sel is
when "00" => y <= i0;
when "01" => y <= i1;
when "10" => y <= i2;
when "11" => y <= i3;
when others => y <= '0'; -- safety default
end case;
end process;
end architecture behavioral;
HARDWARE:
So looks case statement ,converted into hardware where parallel inputs drive and output reach in lesser time.
When if-else will be used and when Case?
Case vs If–Else in VHDL
​
🔹If–Else
​
-
Works well when you need priority logic.
-
Example:
-
In a traffic light controller, if reset = 1 then output must be reset, otherwise check other signals.
-
Here reset must always win over everything else → so if–else is best.
-
-
Synthesizer makes a priority chain (nested muxes).
🔹 Case
​
-
Works best when you have many choices that are mutually exclusive and you want them all equal (no priority).
-
Example:
-
In a multiplexer, sel = 00/01/10/11 decides which input goes to output.
-
No input has priority; all are equal → so case is best.
-
-
Synthesizer makes a single balanced mux (faster, cleaner).
Note: I hope students, you have caught idea of case and if else in hardware and coding approach.