Concurrent statement: Parallel Statement
In VHDL, a concurrent statement is just like a continuous assignment in Verilog, where signals are directly driven and represent pure combinational logic. All concurrent statements run at the same time, meaning multiple outputs are driven in parallel just like wires in hardware. This way, the hardware is generated in parallel and the outputs update together whenever the inputs change.
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In VHDL, concurrent statements are written outside the process. They are always active and update outputs whenever inputs change. In Verilog, this is the same as using an assign statement. Both describe combinational hardware.
VHDL Example (Concurrent Statement)
architecture rtl of example is
signal a, b, y : std_logic;
begin
y <= a and b; -- concurrent statement
end architecture;
Verilog Example (Continuous Assignment)
module example(input a, input b, output y);
assign y = a & b; // continuous assignment
Endmodule
Here in hardware only and gate will be generated
What about delta delay in Concurrent statement?
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Concurrent statements (outside processes)
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When you write assignments directly in the architecture, like this:
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b <= a;
c <= b;
In VHDL, concurrent statements look like they all run at the same time as above, but in reality below, the simulator must decide the order of updates. For example, if you write b <= a; and c <= b; as concurrent statements, it can be confusing which update should happen first. To avoid this problem, VHDL uses the concept of delta delay. Delta delay makes sure that the simulator updates signals step by step in a controlled order. So, even though the code looks parallel, the simulator actually runs updates in small sequential steps using delta delays. This way, the outputs are always correct and consistent.
These look like they happen in parallel and are always active in hardware.
But in simulation, the delta delay is still there to keep things in the correct order.
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If a changes, the simulator first updates b in one delta cycle, and then updates c in the next delta cycle.
This way, dependencies are resolved properly, even though the code looks parallel.
Extra Tips
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Execution:
In VHDL, a process executes sequentially. This means one statement runs after the other, step by step. On the other hand, concurrent statements in an architecture execute simultaneously, just like hardware wires and gates working in parallel.
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Delta Delay:
Inside a process, statements execute one by one, so delta delays are not explicitly visible. In concurrent statements, the simulator uses delta delay internally to maintain the correct order of updates. It can be a bit confusing for beginners, but essentially it only affects how the simulator schedules events.
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Sensitivity:
A process requires a sensitivity list. This means the process only triggers when one of the signals in the list changes. Concurrent statements, however, are always “active” and automatically respond whenever their input signals change.
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Hardware Mapping:
Sequential process code usually maps to sequential hardware like flip-flops. Concurrent statements represent combinational or parallel hardware, like AND/OR gates or multiplexers that work at the same time.
Interview Questions:
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Q: If I send a to b and c to d, do they both update at the same time no matter what delta delay is?
Yes! Both updates happen at the same simulation time.
For example:
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b <= a;
d <= c;
If a changes at 10 ns, then b gets updated at 10 ns.
If c changes at 10 ns, then d gets updated at 10 ns.
Both assignments are independent of each other, so from the outside (waveform or hardware view), b and d update at the same instant.
The simulator may internally schedule them in separate delta cycles, but you never see that difference in the waveform. Delta cycles are just bookkeeping inside the simulator.
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Q: But if I send a to b and then b to c, is the situation different?
Yes, this is where delta delay really shows its role.
For example:
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b <= a;
c <= b;
This is a chain of dependencies: a → b → c.
Imagine a goes from '0' to '1' at 10 ns.
Here’s what the simulator does:
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10 ns, delta 0: The simulator sees that a changed.
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10 ns, delta 1: It updates b with the new value of a.
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10 ns, delta 2: It updates c with the new value of b.
So both b and c look like they changed at 10 ns in the waveform, but internally the simulator needed two delta cycles: one for b and another for c.