Objects
In VHDL, an object is anything that can hold a value and can be used in a design.
Types of Objects in VHDL
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Signal
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Represents physical wires or connections in hardware.
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Updated with a delay (event scheduling).
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In VHDL, signals are the most important type of object. You can think of them as wires in hardware that exist inside an entity or DUT (Design Under Test). These signals physically connect different components within the architecture. When a signal changes, the new value does not appear instantly at the output; instead, it is updated after a very tiny time called a delta delay. This means the output reflects the input change only after this small, simulation-internal delay.
Think of it like a “one step later” effect in the simulation timeline. This delta delay exists only in simulation, not in real hardware.​
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Signal is keyword of VHDL
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Suppose at time t, a changes from '0' to '1'.
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The output c does not update immediately at the exact same simulation time.
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Instead, it updates after one delta cycle. This ensures the simulator correctly models signal propagation order.
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If there is no delta physically, then why is there any delta in simulation, it is not there in Verilog?
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Delta delay is a simulation-specific concept in VHDL. It does not exist in real hardware. In actual circuits, wires do not have a “delta” delay—signals propagate instantly, except for the real physical propagation delay of the devices and interconnects. The idea of delta delay only appears in simulation to help the VHDL engine keep events in the correct order.
The reason it is needed is that VHDL uses a discrete-event simulation model. When multiple signals change at the same simulation time, the simulator has to decide in what order to update them. Delta delay represents an infinitesimally small step forward in simulation time. It allows the simulator to update one signal, then use the updated value to calculate another, without advancing the actual simulation clock.
For example, if you have three signals a, b, and c, and you write b <= a; and c <= b;, then when a becomes ‘1’ at time t, the simulator first updates b using a delta delay, and then in the next delta delay step it updates c using the new value of b. Without delta delays, the order of updates would be ambiguous and could cause race conditions.
Verilog does not describe this mechanism explicitly in the same way. In Verilog, continuous assignments to wires propagate values “instantly” in simulation. However, Verilog simulators also use an event scheduling mechanism internally. The difference is that in VHDL the concept of delta delay is made explicit, while in Verilog the scheduling happens behind the scenes without being described as a formal delta delay.
VHDL
architecture dataflow of deltadelay is
signal a, b, c : std_logic;
begin
c <= a and b; -- output c depends on inputs a and b
end architecture;
2.Variable
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​Used inside processes, functions, or procedures.
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Updated immediately (no delay).
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In VHDL, variables are used when we want to update a value instantly, without the delta delay that signals have.
They are helpful inside a process, function, or procedure when you need to do calculations or pass a value from input to output immediately in simulation.
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Unlike signals, variables do not represent real hardware connections or wires. Instead, they act like temporary storage that exists only during simulation inside the process.
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So, variables are mainly for internal calculations, not for modeling clocked or physical hardware behavior.
How actually signals and variables behave inside a Sequential process?
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Imagine you are designing a small digital circuit in VHDL. You have two tools to describe how values move around: signals and variables.
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Think of a signal as a real wire or a flip-flop in the circuit. Whatever you write with a signal, the synthesizer will try to build in hardware. So if you say q <= a and b;, the tool will literally connect gates so that q becomes the logical AND of a and b. Signals are what actually become the physical connections in your chip.
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Now, variables are different. They don’t directly become wires or storage in hardware. Instead, you can think of them as scratch paper that the synthesizer uses while doing a calculation. For example, if you want to compute something step by step inside a process, you can store the intermediate result in a variable. Later, when you finally assign the result to a signal, only that signal becomes real hardware.
VHDL
variable temp : integer := 0;
Variable is a keyword of VHDL and exists inside process only.
Suppose you write:
process(clk)
variable temp : std_logic;
begin
if rising_edge(clk) then
temp := a and b;
q <= temp;
end if;
end process;
Here’s what happens in the “story”:
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At the rising edge of the clock, the simulator immediately gives temp the value of a and b.
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Then temp is assigned to the signal q.
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But when the synthesizer reads this, it doesn’t actually build a new piece of hardware called temp. Instead, it sees that q is just a and b stored on the rising edge of the clock, so it builds only one flip-flop for q with a and b connected through an AND gate.
In other words, the variable was just a helper for the code, but the final signal assignment is what turned into hardware.
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In a combinational process, the same thing happens. If you use a variable to choose between two inputs, the synthesizer just makes a multiplexer in hardware. The variable disappears, and only the logic that drives the signal remains.
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Inside functions or procedures, variables are even more temporary. They are like notes you write down while solving a math problem. Once the final answer is written onto a signal, the notes are thrown away.
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So the story ends like this: signals are the real hardware — the gates and flip-flops you can point to on a chip. Variables are only shortcuts to describe logic more easily, and they vanish once the synthesizer figures out what hardware to build.
How actually Signals and variables behave in combinational logic?
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If there is no clocked process (i.e. a purely combinational process or concurrent code), then variables and signals still behave differently, but the effect looks a bit different.
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A variable inside a combinational process updates immediately in simulation, just like in a clocked process. It takes the new value as soon as the statement is executed.
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A signal inside the same process does not update immediately. It is scheduled for the next delta cycle. That means within the same process execution, if you read it again, you’ll still see the old value until the process suspends and reactivates.
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Here, x will instantly hold the value of a and b when the process executes.
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y will only update after the delta delay once the process suspends, so if you try to use y again within the same process execution, you’ll still see its old value.
So yes, even without a clock, variables = immediate update and signals = scheduled update (delta cycle later).
Example:
process(a, b)
variable x : std_logic;
signal y : std_logic;
begin
x := a and b;
y <= a and b;
end process;
3. Constant​​
Holds a fixed value that cannot be changed.
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Example
constant WIDTH : integer := 8;
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A constant makes the code readable, reusable, and less error-prone.
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It avoids magic numbers in code.
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It helps in parameterizing designs (like word size, clock frequency, memory depth).
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Constants are same as parameters in Verilog.
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4. File​
Used to read/write data from/to external files during simulation.​​​​
Example
file data_file : text open read_mode is "input.txt";
Important Clarifications
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For files:
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The file object is declared with a file type, for example:
type text_file is file of string;
file log_file : text_file open write_mode is "output.txt";
Here:
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text_file is the file type (a special predefined type or user-defined file type).
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log_file is the file object.
So the direct answer:
File is an object.
But every file object must be declared using some file type (just like signals are declared with a data type).
We have already studied in Data types and Objects both.