Structural Modelling
Structural modeling is used when the design becomes more complex, such as in a large chip that contains many blocks.
​
Instead of writing everything in one place, we divide the design into smaller modules (blocks).
Inside a bigger block, we use these smaller blocks as components and instantiate them.
​
Then, we connect these blocks together. This process of connecting signals between the ports of different blocks is called
port mapping.​
Port Map:
Port mapping is a way of writing code where we connect signals from the outer design to the ports of an inner component.
The inner module is considered encapsulated inside the outer module.
The port names inside the inner module are called formal signals, and the signals in the outer module are called actual signals.
In a port map statement, the formal port is written on the left and the actual signal on the right, which simply shows which port is being connected.
The actual direction of data flow is determined by the mode of the formal port (in, out, or inout).
If the port is an input, the value flows from the actual to the formal, and if the port is an output, the value flows from the formal to the actual.
This ensures that data moves correctly between the inner component and the outer design.
Syntax:
formal => actual
And gate code:
VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and_gate is
port (
A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC
);
end entity;
architecture rtl of and_gate is
begin
Y <= A and B;
end architecture;
TOP MODULE:
VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top_module is
port (
X1 : in STD_LOGIC;
X2 : in STD_LOGIC;
Z : out STD_LOGIC
);
end entity;
architecture structural of top_module is
begin
-- Port Mapping
U1: entity work.and_gate
port map (
A => X1, -- formal A (inner input) gets value from outer signal X1
B => X2, -- formal B (inner input) gets value from outer signal X2
Y => Z -- formal Y (inner output) drives outer signal Z
);
end architecture;
Inside the top module, the AND gate is encapsulated, and in the port map the connection is written from the formal to the actual.
VHDL
port map (
A => X1, -- formal A (inner input) gets value from outer signal X1
B => X2, -- formal B (inner input) gets value from outer signal X2
Y => Z -- formal Y (inner output) drives outer signal Z
);
Real Time Example For Structural Modeling:
ALU Chip Example:
​
This is the code for a 4-bit small ALU where, when ALU_Sel is 00, it performs addition, when it is 01 it performs the AND operation, when it is 10 it performs the OR operation, and for any other value the result and carry-out are both set to zero.
​
ALU Code:
VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity alu_4bit is
port (
A : in STD_LOGIC_VECTOR(3 downto 0);
B : in STD_LOGIC_VECTOR(3 downto 0);
ALU_Sel : in STD_LOGIC_VECTOR(1 downto 0);
Result : out STD_LOGIC_VECTOR(3 downto 0);
Cout : out STD_LOGIC
);
end entity;
architecture structural of alu_4bit is
signal add_out : STD_LOGIC_VECTOR(3 downto 0);
signal and_out : STD_LOGIC_VECTOR(3 downto 0);
signal or_out : STD_LOGIC_VECTOR(3 downto 0);
signal add_c : STD_LOGIC;
begin
U_ADD : entity work.adder_4bit
port map (A => A, B => B, SUM => add_out, Cout => add_c);
U_AND : entity work.and_4bit
port map (A => A, B => B, Y => and_out);
U_OR : entity work.or_4bit
port map (A => A, B => B, Y => or_out);
-- Structural MUX via with-select
with ALU_Sel select
Result <= add_out when "00",
and_out when "01",
or_out when "10",
(others => '0') when others;
-- Carry out only meaningful for ADD
Cout <= add_c when ALU_Sel = "00" else '0';
end architecture;
4 bit adder code inner side Full adder:
VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity adder_4bit is
port (
A : in STD_LOGIC_VECTOR(3 downto 0);
B : in STD_LOGIC_VECTOR(3 downto 0);
SUM : out STD_LOGIC_VECTOR(3 downto 0);
Cout : out STD_LOGIC
);
end entity;
architecture structural of adder_4bit is
signal c1, c2, c3 : STD_LOGIC;
begin
FA0: entity work.full_adder
port map (A => A(0), B => B(0), Cin => '0', SUM => SUM(0), Cout => c1);
FA1: entity work.full_adder
port map (A => A(1), B => B(1), Cin => c1, SUM => SUM(1), Cout => c2);
FA2: entity work.full_adder
port map (A => A(2), B => B(2), Cin => c2, SUM => SUM(2), Cout => c3);
FA3: entity work.full_adder
port map (A => A(3), B => B(3), Cin => c3, SUM => SUM(3), Cout => Cout);
end architecture;
4 bit and gate code:
VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and_4bit is
port (
A : in STD_LOGIC_VECTOR(3 downto 0);
B : in STD_LOGIC_VECTOR(3 downto 0);
Y : out STD_LOGIC_VECTOR(3 downto 0)
);
end entity;
architecture rtl of and_4bit is
begin
Y <= A and B;
end architecture;
4 bit OR gate code:
VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity or_4bit is
port (
A : in STD_LOGIC_VECTOR(3 downto 0);
B : in STD_LOGIC_VECTOR(3 downto 0);
Y : out STD_LOGIC_VECTOR(3 downto 0)
);
end entity;
architecture rtl of or_4bit is
begin
Y <= A or B;
end architecture;
