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SR Latch (NOR-based)
Introduction
An SR latch stores one bit of information using Set (S) and Reset (R) inputs. It is level-sensitive and implemented using NOR gates in this version.
Problem Statement
Design an SR latch that sets the output when S is high, resets the output when R is high, and holds the output when both S and R are low.
Specifications
-
Inputs: S (Set), R (Reset)
-
Outputs: Q, Qbar (Complement)
-
Invalid state occurs when S=1 and R=1 simultaneously
Truth Table
Verilog RTL Code
Verilog
module sr_latch_nor (
input wire S,
input wire R,
output wire Q,
output wire Qbar
);
assign Q = ~(R | Qbar);
assign Qbar = ~(S | Q);
endmodule
Testbench Code
Verilog
module tb_sr_latch_nor();
reg S, R;
wire Q, Qbar;
sr_latch_nor tb_sr_latch (.S(S), .R(R), .Q(Q), .Qbar(Qbar));
initial begin
$monitor("Time=%0t | S=%b R=%b | Q=%b Qbar=%b", $time, S, R, Q, Qbar);
S = 0; R = 0;
#5 S = 1; R = 0;
#5 S = 0; R = 1;
#5 S = 0; R = 0;
#5 S = 1; R = 1; // Invalid
#5 $finish;
end
endmodule
Interview Questions & Answers
Q1. Why is the state when S=1 and R=1 considered "invalid" in a NOR-based SR latch?
Answer:
In a NOR SR latch, when both inputs are 1, both NOR gates output 0. This breaks the complementary nature of Q and Q′ because both will be 0 simultaneously, which is impossible for a proper bistable storage element. This state also causes unpredictability when inputs return to 0, because the final state depends on gate delays.
Q2. What happens if S and R are both kept at 1 for a long period of time?
Answer:
Q and Q′ will both remain at 0 during that time, which violates the expected behavior (one should be 1, the other 0). This can cause logic errors in connected circuits because the latch stops behaving as a proper memory element.
Q3. Why can a NOR-based SR latch become metastable?
Answer:
If S and R change very close to each other in time, the internal feedback paths might struggle to settle into a stable state. This can cause Q and Q′ to oscillate briefly or remain at intermediate voltages, leading to unpredictable outputs.
Q4. If S=1 for only 1 ns in a NOR-based latch, will Q always change?
Answer:
Not necessarily. If the pulse width is shorter than the latch’s propagation delay, the internal gates may not register it, so Q might remain unchanged. This is why designers ensure pulses are longer than the device’s minimum set/reset pulse width.
Q5. How can you modify a NOR-based SR latch to remove the invalid state?
Answer:
Replace the two separate S and R inputs with a single D input and feed ~D to R and D to S. This creates a D latch, which eliminates the S=1, R=1 invalid case entirely.
Q6. Can you cascade two SR latches to create a flip-flop?
Answer:
Yes. By connecting two SR latches in a master–slave configuration and using opposite clock phases for enabling, you can create an edge-triggered flip-flop. This is how early D flip-flops were built.
Q7. Why do SR latches respond immediately to input changes when enabled?
Answer:
They are level-sensitive, meaning their outputs change as soon as inputs change, without waiting for a clock edge. This makes them faster than flip-flops but also more prone to glitches.
Q8. What happens if both S and R go from 0 to 1 at exactly the same time and then both go back to 0?
Answer:
The latch may enter a race condition where the final state depends on slight differences in gate propagation delays. In practice, one side will “win” and set Q accordingly, but which side wins is unpredictable.
Q9. Why is the NOR version of an SR latch called an "active-high" latch?
Answer:
Because giving a high (logic 1) signal to S or R actively sets or resets the latch. In contrast, NAND-based SR latches are active-low.
Q10. If S is kept high and R is pulsed high briefly, what happens?
Answer:
The latch will still remain in the set state (Q=1) because the moment R goes low again, S being high forces Q back to 1. The brief reset attempt is overridden by the still-active set input.
Q11. Can an SR latch be used to debounce a switch?
Answer:
Yes. When connected properly, it can store a stable state until the switch finishes bouncing, preventing multiple unwanted toggles from propagating to the next stage of the circuit.
Q12. Why is it not safe to use SR latches in high-speed synchronous designs without control logic?
Answer:
Because their level-sensitive nature allows multiple changes during one enable period, causing timing violations, race conditions, and unpredictable data capture.
Q13. How would you reset an SR latch at power-up to a known state?
Answer:
By applying a short high pulse to the R input after power is applied. This forces Q=0 and Q′=1, ensuring the latch starts in a known condition.
Q14. If Q′ is accidentally used as the main output in a circuit, what issues can arise?
Answer:
The logic will be inverted from what was intended, which might cause errors in downstream logic. Timing could also differ slightly due to propagation differences between Q and Q′.
Q15. In a NOR SR latch, can the outputs Q and Q′ ever be the same?
Answer:
Yes, but only in the invalid state when S=1 and R=1. In all valid cases, Q and Q′ are exact complements of each other.
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