JK Latch

Introduction

A JK latch overcomes the invalid state problem of the SR latch. It has inputs J and K, and can set, reset, or toggle the output based on their values.

Problem Statement

Design a JK latch that:

Sets the output when J=1 and K=0

Resets the output when J=0 and K=1

Toggles the output when J=1 and K=1

Holds the output when J=0 and K=0

Specifications

Inputs: J, K, EN (Enable)

Output: Q

Operation: Set when J=1, Reset when K=1, Toggle when both are 1

Truth Table

Verilog RTL Code

Verilog

module jk_latch (
input wire J,
input wire K,
input wire EN,
output reg Q
);
always @ (J or K or EN) begin
if (EN) begin
case ({J,K})
2'b00: Q <= Q;
2'b01: Q <= 0;
2'b10: Q <= 1;
2'b11: Q <= ~Q;
endcase
end
end
endmodule

Testbench Code

Verilog

module tb_jk_latch();
reg J, K, EN;
wire Q;

jk_latch tb_jk_latch (.J(J), .K(K), .EN(EN), .Q(Q));

initial begin
$monitor("Time=%0t | EN=%b J=%b K=%b | Q=%b", $time, EN, J, K, Q);
EN = 0; J = 0; K = 0;
#5 EN = 1; J = 1; K = 0;
#5 J = 0; K = 1;
#5 J = 1; K = 1;
#5 EN = 0; J = 0; K = 0;
#5 $finish;
end
endmodule

Interview Questions & Answers

Q1. Why was the JK latch invented when SR latches already existed?

Answer:
The JK latch solves the invalid state problem of the SR latch. In SR, S=1 and R=1 causes both outputs to be 0, breaking the bistable nature. In a JK latch, J=1 and K=1 makes the output toggle instead, ensuring every input combination is valid.

Q2. Why does the JK latch still have race condition problems even though it solves the invalid state?

Answer:

Because it’s still level-sensitive if J=K=1 while the latch is enabled, the output keeps toggling as long as inputs remain 1, which can happen multiple times during one enable window. This is the race-around condition

Q3. How can the race-around condition in a JK latch be removed?

Answer:

Use edge-triggering instead of level-sensitivity. This is usually done by cascading two latches (master–slave) so that output only changes once per clock edge, not continuously during the high phase.

Q4. If a JK latch has J=K=1 and enable is high for 20 ns, with a propagation delay of 5 ns, how many toggles occur?

Answer:

At most, 4 toggles (20 ÷ 5 = 4). In practice, slight delays in feedback paths may reduce this number. This is the mathematical reason race-around happens.

Q5. Why is the JK latch sometimes called a "universal latch"?

Answer:

Because it can replicate the behavior of SR, D, and T latches simply by tying inputs appropriately:

SR: J as Set, K as Reset.

D: Connect D to J, ~D to K.

T: Connect T to both J and K.

Q6. If J=0 and K=1, why does the output always reset regardless of previous state?

Answer:

Because K=1 means the “reset path” is active, and with J=0, there’s no set signal to counter it. Once the latch is enabled, Q goes to 0 and stays there.

Q7. How does feedback wiring differ between an SR latch and a JK latch?

Answer:

In an SR latch, S and R are independent inputs. In a JK latch, J and K inputs are ANDed with the opposite output before going into the latch, creating feedback paths that allow toggling instead of invalid states.

Q8. Can a JK latch be used for frequency division?

Answer:

Yes. If J=K=1 and race-around is controlled (e.g., using edge-triggering), the output toggles once per clock pulse, dividing the input frequency by 2.

Q9. Why might a JK latch be unsuitable for purely combinational circuits?

Answer:

Because it has memory and its output depends not only on the current inputs but also on its previous state. This violates the principle of combinational logic (output only based on current inputs).

Q10. In high-speed designs, why might designers avoid using JK latches directly?

Answer:

Because controlling the enable period to avoid race-around becomes harder as clock speeds increase. Designers often use JK flip-flops (edge-triggered) instead.

Q11. What happens if J=K=0 in a JK latch for a very long time?

Answer:

The output simply holds its last state indefinitely. This is the memory mode of the latch.

Q12. How does propagation delay affect toggling frequency in JK latches?

Answer:

The toggling speed is limited by the latch’s propagation delay. If the enable time is shorter than 2×delay, toggling may not happen at all, preventing race-around but also limiting maximum speed.

Q13. If a JK latch is initialized to Q=1, and then J=0, K=1 is applied with enable high, what will be the next state?

Answer:

It will reset to Q=0 immediately after the propagation delay, regardless of previous high state.

Q14. Why is the JK latch often taught after SR and D latches?

Answer:

Because it builds on the concepts of both. Students first understand basic set/reset storage, then controlled data input (D latch), before moving to the more versatile JK latch which combines these behaviors.

Q15. How do NAND-based and NOR-based JK latch designs differ in active level?

Answer:

NOR-based designs are active-high (inputs active at logic 1), while NAND-based designs are active-low (inputs active at logic 0). Designers choose based on logic family compatibility.

JK Latch

Introduction

Problem Statement

Specifications

Truth Table

Verilog RTL Code

Testbench Code

Interview Questions & Answers

Because it’s still level-sensitive if J=K=1 while the latch is enabled, the output keeps toggling as long as inputs remain 1, which can happen multiple times during one enable window. This is the race-around condition

​

​

Q3. How can the race-around condition in a JK latch be removed? Answer:

Use edge-triggering instead of level-sensitivity. This is usually done by cascading two latches (master–slave) so that output only changes once per clock edge, not continuously during the high phase.

​​

​

Q4. If a JK latch has J=K=1 and enable is high for 20 ns, with a propagation delay of 5 ns, how many toggles occur?

Answer:

At most, 4 toggles (20 ÷ 5 = 4). In practice, slight delays in feedback paths may reduce this number. This is the mathematical reason race-around happens.

​​

​

Q5. Why is the JK latch sometimes called a "universal latch"?

​

Answer:

Because it can replicate the behavior of SR, D, and T latches simply by tying inputs appropriately:

SR: J as Set, K as Reset.

D: Connect D to J, ~D to K.

T: Connect T to both J and K.

​

​

Q6. If J=0 and K=1, why does the output always reset regardless of previous state?

​

Answer:

Because K=1 means the “reset path” is active, and with J=0, there’s no set signal to counter it. Once the latch is enabled, Q goes to 0 and stays there.

​

​

Q7. How does feedback wiring differ between an SR latch and a JK latch?

​

Answer:

In an SR latch, S and R are independent inputs. In a JK latch, J and K inputs are ANDed with the opposite output before going into the latch, creating feedback paths that allow toggling instead of invalid states.

​

​

Q8. Can a JK latch be used for frequency division?

Answer:

Yes. If J=K=1 and race-around is controlled (e.g., using edge-triggering), the output toggles once per clock pulse, dividing the input frequency by 2.

​

​

Q9. Why might a JK latch be unsuitable for purely combinational circuits?

​

Answer:

Because it has memory and its output depends not only on the current inputs but also on its previous state. This violates the principle of combinational logic (output only based on current inputs).

​

​

Q10. In high-speed designs, why might designers avoid using JK latches directly?

Answer:

Because controlling the enable period to avoid race-around becomes harder as clock speeds increase. Designers often use JK flip-flops (edge-triggered) instead.

​

​

Q11. What happens if J=K=0 in a JK latch for a very long time?

​

Answer:

The output simply holds its last state indefinitely. This is the memory mode of the latch.

​

​

Q12. How does propagation delay affect toggling frequency in JK latches?

​

Answer:

The toggling speed is limited by the latch’s propagation delay. If the enable time is shorter than 2×delay, toggling may not happen at all, preventing race-around but also limiting maximum speed.

​

​

Q13. If a JK latch is initialized to Q=1, and then J=0, K=1 is applied with enable high, what will be the next state?

​

Answer:

It will reset to Q=0 immediately after the propagation delay, regardless of previous high state.

​

​

Q14. Why is the JK latch often taught after SR and D latches?

​

Answer:

Because it builds on the concepts of both. Students first understand basic set/reset storage, then controlled data input (D latch), before moving to the more versatile JK latch which combines these behaviors.

​

Q3. How can the race-around condition in a JK latch be removed?

Answer: